def setFreq(self, freq): # Hz
     if FREQ_MIN <= float(freq) <= FREQ_MAX:
         command_l, adjustedFreq = self.formatCommand("freq")
         #print "Channel %d frequency %f adjusted to %f" % (self.channel, freq, adjustedFreq)
         x24bitParallelPort.send(command_l)
     else:
         print "Freqency out of range (0Hz-262,144Hz)", freq
Esempio n. 2
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 def sendStateToFPGA(self):
     channel_bin_str = '{0:05b}'.format(self.channel)[::-1]
     osc_bin_str = ('{0:028b}'.format(int(FPGA_CLOCK_SPEED_DIVIDED/self.freq)))[::-1]
     #print "period: ", int(FPGA_CLOCK_SPEED_DIVIDED/self.freq)
     #print "binary: ", osc_bin_str
     freq_msb = osc_bin_str[0:17]
     freq_lsb = osc_bin_str[17:28]
     dutyCycle_bin_str = "11111111111" if self.dutyCycle > 99 else '{0:011b}'.format(int((self.dutyCycle*0.32)+0.5))[::-1]
     modeSelector_bin_str = 0
     x24bitParallelPort.send(list("%s%s%s"%(modeSelector_bin_str,channel_bin_str,freq_msb)))
     #print "word 1 sent: %s%s%s" % (modeSelector_bin_str,channel_bin_str,freq_msb) 
     modeSelector_bin_str = 1
     x24bitParallelPort.send(list("%s%s%s"%(modeSelector_bin_str,freq_lsb, dutyCycle_bin_str)))
Esempio n. 3
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def _sendToFPGA(channel, dutyCycle, freq):
    fpgaCycles = _convertFreqToFpga(channels[channel]["freq"])
    dutyCycle127 = _convertPercentTo7Bit(channels[channel]["dutyCycle"])
    channel_ba = _dec2bin(channel, 5)
    dutyCycle_ba = _dec2bin(dutyCycle127, 7)
    fpgaCycles_ba = _dec2bin(fpgaCycles, 34)
    # Assuming MSB
    frame_ba = "%s%s%s" % (channel_ba, dutyCycle_ba, fpgaCycles_ba)

    word1 = "%s%s" % (frame_ba[0:23], "0")
    word2 = "%s%s" % (frame_ba[23:46], "1")
    #print channel, dutyCycle, freq
    print channel_ba, dutyCycle_ba, fpgaCycles_ba
    print word1, word2
    x24bitParallelPort.send(word1)
    x24bitParallelPort.send(word2)
Esempio n. 4
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 def sendStateToFPGA(self, freq_b, ds_b):
     channel_bin_str = '{0:05b}'.format(self.channel)[::-1]
     if freq_b:
         modeSelector_bin_str = "0"
         osc_bin_str = ('{0:017b}'.format(
             int(FPGA_CLOCK_SPEED_DIVIDED / self.freq)))[::-1]
         x24bitParallelPort.send(
             list("%s%s%s" % (modeSelector_bin_str, channel_bin_str,
                              osc_bin_str)))
     if ds_b:
         modeSelector_bin_str = "1"
         dutyCycle_bin_str = "000011" if self.dutyCycle > 99 else '{0:06b}'.format(
             int(max(0,
                     int(self.dutyCycle * 0.32) - 1)))[::-1]
         padding_bin_str = "000000000000"
         x24bitParallelPort.send(
             list("%s%s%s%s" %
                  (modeSelector_bin_str, channel_bin_str,
                   dutyCycle_bin_str, padding_bin_str)))
import sys
import x24bitParallelPort

while True:
    sys.stdout.write("please input a 23-bit binary number")
    input_raw = sys.stdin.readline()
    input_trimmed = input_raw[:-1]
    #input_padded =  '{0:03d}'.format(4)
    if len(input_trimmed) != 23:
        print "input is not 23 bits. try again"
    else:
        x24bitParallelPort.send(list(input_trimmed))
 def setPwm(self, pwm_f): # float%
     if 0.0 <= pwm_f <= 100.0:
         command_l = self.formatCommand("pwm")
         x24bitParallelPort.send(command_l)
     else:
         print "PWM out of range (0.0-100.0)", pwm_f