def run_check_flow(self): # // run check flow always! report_path = self.scripts_options.get("cwd") #if(os.path.abspath(report_path) == os.path.abspath(self.job_dir)):# update by Yzhao1 # report_path = os.path.join(self.job_dir,self.design) if not self.check_rpt: report = "check_flow.csv" else: _check_rpt = xTools.get_abs_path(self.check_rpt, report_path) report_path, report = os.path.split(_check_rpt) check_py = os.path.join(os.path.dirname(__file__), '..', '..', 'tools', 'check', "check.py") check_py = os.path.abspath(check_py) if xTools.not_exists(check_py, "source script file"): return 1 cmd_kwargs = dict() cmd_kwargs["top_dir"] = "--top-dir=%s" % self.job_dir cmd_kwargs["design"] = "--design=%s" % self.design _check_conf = self.scripts_options.get("check_conf") if _check_conf: cmd_kwargs["conf_file"] = "--conf-file=%s" % _check_conf else: cmd_kwargs["conf_file"] = "" cmd_kwargs["report_path"] = "--report-path=%s" % report_path cmd_kwargs["tag"] = "--tag=%s" % self.tag cmd_kwargs["report"] = "--report=%s" % report cmd_kwargs["rerun_path"] = "--rerun-path=%s" % report_path # NEW check flow if self.scripts_options.get("synthesis_only"): _ = self.scripts_options.get("synthesis") if _ == "lse": cmd_kwargs["lse_check"] = "--lse-check" else: cmd_kwargs["synp_check"] = "--synp-check" else: for _ in ("run_par_trace", "run_par", "pushbutton"): if self.scripts_options.get(_): if self.scripts_options.get( "till_map"): # till map has higher priority pass else: cmd_kwargs["partrce_check"] = "--partrce-check" else: for _ in ("run_map", "till_map", "run_map_trace"): if self.scripts_options.get(_): cmd_kwargs["map_check"] = "--map-check" # cmd_line = r"%s %s " % (sys.executable, check_py) for key, value in cmd_kwargs.items(): cmd_line += " %s " % value cmd_line = xTools.win2unix(cmd_line, 0) xTools.say_it(" Launching %s" % cmd_line) sts, text = xTools.get_status_output(cmd_line) xTools.say_it(text) return sts
def merge_conf_options(self): ''' get the conf file setting, and merge them with command options ''' _conf = self.scripts_options.get("conf") if not _conf: _conf = os.path.join(os.path.dirname(sys.argv[0]), "..", "conf") if os.path.isdir(_conf): pass else: if xTools.not_exists(_conf, "Default Configuration Path"): return 1 _conf = os.path.abspath(_conf) self.scripts_options["conf"] = _conf conf_files = glob.glob(os.path.join(_conf, "*.ini")) if not conf_files: xTools.say_it("-Error. Not found any ini file under %s" % _conf) return 1 sts, conf_options = xTools.get_conf_options(conf_files) if sts: return 1 self._merge_options(conf_options) xTools.say_it(self.scripts_options, "Merge User/Default Configuration Options", self.debug)
def run_test_process(self): # synthesize flow if self.synthesis == "synplify": template_file = os.path.join(self.conf, "ice_synthesis", "run_synplify.prj") prj_file = "run_synplify.prj" else: template_file = os.path.join(self.conf, "ice_synthesis", "run_lse.synproj") prj_file = "run_lse.synproj" if xTools.not_exists(template_file, "Template file"): return 1 xTools.generate_file(prj_file, template_file, self.kwargs) if self.synthesis == "synplify": syn_cmd = "%s -prj %s" % (self.synpwrap_exe, prj_file) else: syn_cmd = "%s -f %s" % (self.lse_exe, prj_file) sts = xTools.run_command(syn_cmd, "run_synthesis.log", "run_synthesis.time") if sts: return 1 for command in ("edifparser", "sbtplacer", "packer_drc", "packer", "sbrouter", "netlister", "sbtimer", "bitmap"): sts = self.runit.run_flow(command, self.kwargs) if sts: return sts
def dump_vcd_file(cur_dir=""): if not cur_dir: cur_dir = os.getcwd() if xTools.not_exists(cur_dir, "vcd path"): return 1 for foo in os.listdir(cur_dir): fname, fext = os.path.splitext(foo) if fext.lower() != ".vcd": continue try: vcd_data = Verilog_VCD.parse_vcd(os.path.join(cur_dir, foo)) except: xTools.say_it("Warning. Failed to dump from %s" % (os.path.join(cur_dir, foo))) return vcd_txt = "%s_vcd.txt" % fname dump_file = os.path.join(cur_dir, vcd_txt) xTools.say_it(" Dumping %s to %s" % (foo, vcd_txt)) dump_lines = list() keys = vcd_data.keys() keys.sort() for k in keys: v = vcd_data.get(k) nets = v.get("nets")[0] hier = nets.get("hier") if hier != "sim_top.uut": continue dump_lines.append("-" * 10) nets_keys = nets.keys() nets_keys.sort() dump_lines += ["%s : %s" % (nk, nets.get(nk)) for nk in nets_keys] dump_lines += xTools.distribute_list("time-value", v.get("tv"), 15) xTools.write_file(dump_file, dump_lines)
def run_par_vlg_simulation(self, sim_path): source_file = os.path.join( self.impl_dir, "%s_%s_vo.vo" % (self.project_name, self.impl_name)) if xTools.not_exists(source_file, "Simulation Export Verilog File"): return 1 source_files = [os.path.join("..", source_file)] user_options = dict(run_export_vlg=1) return self._run_simulation(sim_path, source_files, user_options)
def check_exists(self, a_file, comments): if not a_file: xTools.say_it("-Warning. No specified for %s" % comments) return 1, "" new_file = xTools.get_relative_path(a_file, self.src_design) if xTools.not_exists(new_file, comments): return 1, "" return 0, new_file
def _basic_check(self): top_dir = self.cmd_options.get("top_dir") job_dir = self.cmd_options.get("job_dir") design = self.cmd_options.get("design") conf = self.cmd_options.get("conf") # ---------------------- # get design list if design: design = [design] else: design = list() # ---------------------- # get top_dir and design list if top_dir: if xTools.not_exists(top_dir, "Top Source Directory"): return 1 top_dir = os.path.abspath(top_dir) if not design: for item in os.listdir(top_dir): abs_item = os.path.join(top_dir, item) if os.path.isdir(abs_item): design.append(item) else: if not design: t = os.path.split(os.getcwd()) top_dir = t[0] design.append(t[1]) # ---------------------- # check conf value _base_scripts = os.path.abspath(sys.argv[0]) conf_root_path = os.path.dirname(os.path.dirname(_base_scripts)) if not conf: conf = "conf" if os.path.isdir(conf): conf = os.path.abspath(conf) else: conf = os.path.join(conf_root_path, conf) if xTools.not_exists(conf, "Default conf Path"): conf = "" # will use command options only # new values after checking self.cmd_options["top_dir"] = top_dir self.cmd_options["design"] = design if not job_dir: self.cmd_options["job_dir"] = top_dir self.cmd_options["conf"] = conf
def get_target_fmax(self, sdc_file): if not_exists(sdc_file): return "NoTargetFmax" for line in open(sdc_file): line = line.strip() m_tf = self.p_tf.search(line) if m_tf: return m_tf.group(1) return "NoTargetFmax"
def run_map_vhd_simulation(self, sim_path): source_file = os.path.join( self.impl_dir, "%s_%s_mapvho.vho" % (self.project_name, self.impl_name)) if xTools.not_exists(source_file, "Simulation Map VHDL File"): return 1 source_files = [os.path.join("..", source_file)] user_options = dict(run_map_vhd=1) return self._run_simulation(sim_path, source_files, user_options)
def get_clocks_from_sta_summary(sta_summary): if not_exists(sta_summary, "sta report summary file"): return clocks = set() for line in open(sta_summary): line = line.strip() m_clock = p_clock.search(line) if m_clock: clocks.add(m_clock.group(1)) clock_list = list(clocks) clock_list.sort(key=str.lower) return clock_list
def merge_file_options(self): user_file = self.scripts_options.get("file") if not user_file: return elif user_file: if xTools.not_exists(user_file, "User Configuration File"): return 1 sts, file_options = xTools.get_conf_options(user_file) if sts: return 1 self._merge_options(file_options) xTools.say_it(self.scripts_options, "Merge User Configuration Options", self.debug)
def get_clocks_from_fit_rpt(fit_rpt): if not_exists(fit_rpt, "fit rpt file"): return clocks_a = get_a_clocks(fit_rpt) cs_p, cs_clk_list = re.compile("^; Control Signals\s+;$"), [ "clock", "latch enable", "global clock" ] clocks_b_cs = get_b_clocks(fit_rpt, cs_p, cs_clk_list) clocks = list() for foo in (clocks_a, clocks_b_cs): for bar in foo: if bar not in clocks: clocks.append(bar) return clocks
def scan_report(self): scan_py = os.path.join(os.path.dirname(__file__), '..', '..', 'tools', 'scan_report', "bin", "run_scan_lattice_step_general_case.py") if xTools.not_exists(scan_py, "Scan scripts"): return 1 tag_dir = os.getcwd() design_dir, tag = os.path.split(tag_dir) job_dir, design = os.path.split(design_dir) args = "special-structure=%s --job-dir=%s --design=%s" % (tag, job_dir, design) cmd_line = "%s %s %s" % (sys.executable, scan_py, args) xTools.say_it(" Launching %s" % cmd_line) sts, text = xTools.get_status_output(cmd_line) xTools.say_raw(text)
def run_syn_vhd_simulation(self, sim_path): if self.synthesis == "lse": xTools.say_it( "Error. when synthesis is lse, --run-syn-vlg supported only") return else: xTools.say_it("TODO: Not support post synplify simulation flow.") source_file = os.path.join( self.impl_dir, "%s_%s_mapvho.vho" % (self.project_name, self.impl_name)) if xTools.not_exists(source_file, "Post synthesis Simulation VHDL File"): return 1 source_files = [os.path.join("..", source_file)] user_options = dict(run_syn_vhd=1) return self._run_simulation(sim_path, source_files, user_options)
def check_iCEcube(self): iCEcube_path = self.flow_options.get("icecube_path") if xTools.not_exists(iCEcube_path, "iCEcube path"): return 1 self.ice_root_path = iCEcube_path self.ice_opt_path = xTools.win2unix( os.path.join(iCEcube_path, "sbt_backend", "bin", "win32", "opt")) self.lse_exe = xTools.win2unix( os.path.join(iCEcube_path, "LSE", "bin", "nt", "synthesis.exe")) self.synpwrap_exe = xTools.win2unix( os.path.join(self.ice_opt_path, "synpwrap", "synpwrap.exe")) os.environ["FOUNDRY"] = xTools.win2unix( os.path.join(iCEcube_path, "LSE")) os.environ["SYNPLIFY_PATH"] = xTools.win2unix( os.path.join(iCEcube_path, "synpbase"))
def run_lse_flow(self, src_files, kwargs): synthesis_cmd = self.section_cmd.get("synthesis") new_src_files = self.get_lse_source_files(src_files) if not self.run_synthesis: return if synthesis_cmd: sts, lse_cmd = xTools.get_cmd(synthesis_cmd, dict(src_files=new_src_files)) if sts: return 1 # sometimes the user do NOT use -f for specify the source files lse_cmd = re.sub("\s+", " ", lse_cmd) sts = xTools.run_command(lse_cmd, "my_run_lse.log", "my_run_lse.time") return sts # --------------------- if not self.synp_goal: self.synp_goal = "Timing" else: self.synp_goal = self.synp_goal.capitalize() kwargs["goal"] = self.synp_goal _tm = "" if self.top_module: _tm = "-top %s" % self.top_module kwargs["top_module"] = _tm if self.inc_path: _inc_path = xTools.to_abs_list(self.inc_path, self.src_design) else: _inc_path = list() _inc_path.append(xTools.win2unix(os.getcwd())) kwargs["search_path"] = '"%s"' % '" '.join(_inc_path) kwargs["source_files"] = new_src_files synproj_template = os.path.join(self.conf, "synthesis", "run_lse.synproj") if xTools.not_exists(synproj_template, "LSE Project Template"): return 1 lse_synproj_file = "run_lse.synproj" xTools.generate_file(lse_synproj_file, synproj_template, kwargs) lse_cmd = "synthesis -f %s" % lse_synproj_file sts = xTools.run_command(lse_cmd, "my_run_lse.log", "my_run_lse.time") return sts
def run_syn_vlg_simulation(self, sim_path): if self.synthesis == "lse": glob_pattern = os.path.join(self.impl_dir, "*_prim.v") source_files = glob.glob(glob_pattern) if source_files: source_file = source_files[0] else: xTools.say_it( "Error. Not found _prim.v file for post lse simulation flow" ) return 1 else: xTools.say_it("TODO: Not support post synplify simulation flow.") return if xTools.not_exists(source_file, "Post synthesis Simulation Verilog File"): return 1 source_files = [os.path.join("..", source_file)] user_options = dict(run_syn_vlg=1) return self._run_simulation(sim_path, source_files, user_options)
def process(self): sim_vendor_bin = os.getenv("SIM_VENDOR_BIN") if xTools.not_exists(sim_vendor_bin, "Simulation tool bin path"): return 1 self.sim_vendor_bin = xTools.win2unix(sim_vendor_bin) if self.flatten_options(): # ///////////////// # do the implementation flow pass # return 1 # #run Your PUSHBUTTON FLOW firstly user_options = self.get_user_options() sts = 0 task_list = xLattice.get_task_list(self.flow_options, user_options) if task_list: # sts = xLattice.run_ldf_file("run_firstly.tcl", self.final_ldf_file, task_list) # updated for new log name sts = xLattice.run_ldf_file("foundry_flow.tcl", self.final_ldf_file, task_list) if sts: xTools.say_it( "-Warning. errors found in normal implementation flow") for (sim_type, sim_path, sim_func) in ( (self.sim_rtl, "sim_rtl", self.run_rtl_simulation), (self.sim_syn_vhd, "sim_syn_vhd", self.run_syn_vhd_simulation), (self.sim_syn_vlg, "sim_syn_vlg", self.run_syn_vlg_simulation), (self.sim_map_vhd, "sim_map_vhd", self.run_map_vhd_simulation), (self.sim_map_vlg, "sim_map_vlg", self.run_map_vlg_simulation), (self.sim_par_vhd, "sim_par_vhd", self.run_par_vhd_simulation), (self.sim_par_vlg, "sim_par_vlg", self.run_par_vlg_simulation), ): if sim_type: sts = sim_func(sim_path) if self.run_simrel: sts = self.run_simrel_flow() return sts
def flatten_options(self): foundry_path = os.getenv("FOUNDRY") if xTools.not_exists(foundry_path, "Foundry Path"): return 1 self.src_design = self.flow_options.get("src_design") self.dst_design = self.flow_options.get("dst_design") self.synthesis = self.flow_options.get("synthesis") if not self.synthesis: self.synthesis = "synplify" self.sim_rtl = xTools.get_true(self.flow_options, "sim_rtl") self.sim_syn_vlg = xTools.get_true(self.flow_options, "sim_syn_vlg") self.sim_syn_vhd = xTools.get_true(self.flow_options, "sim_syn_vhd") self.sim_map_vlg = xTools.get_true(self.flow_options, "sim_map_vlg") self.sim_map_vhd = xTools.get_true(self.flow_options, "sim_map_vhd") self.sim_par_vlg = xTools.get_true(self.flow_options, "sim_par_vlg") self.sim_par_vhd = xTools.get_true(self.flow_options, "sim_par_vhd") self.sim_all = xTools.get_true(self.flow_options, "sim_all") self.simrel_path = self.flow_options.get("simrel_path") self.run_simrel = self.flow_options.get("run_simrel") self.pmi = xTools.get_true(self.flow_options, "pmi") self.lst_precision = self.flow_options.get("lst_precision") if self.sim_all: self.sim_rtl = self.sim_map_vhd = self.sim_map_vlg = self.sim_par_vhd = self.sim_par_vlg = 1 self.sim_syn_vlg = 1 if self.sim_syn_vlg: self.sim_syn_vhd = 0 others_path = self.flow_options.get("others_path") if others_path: others_path = os.path.join(self.src_design, others_path) if os.path.isdir(others_path): self.others_path = others_path else: self.others_path = "" sim_section = self.flow_options.get("sim") if not sim_section: xTools.say_it("-Error. Not any simulation settings found.") return 1 self.dev_lib = sim_section.get("dev_lib") self.pri_lib = sim_section.get("pri_lib") self.src_lib = sim_section.get("src_lib") diamond = os.path.dirname(foundry_path) self.diamond = diamond = xTools.win2unix(diamond) if self.pri_lib: self.pri_lib = re.sub('\$diamond', diamond, xTools.win2unix(self.pri_lib, 0)) else: self.pri_lib = "work" if self.src_lib: self.src_lib = re.sub('\$diamond', diamond, xTools.win2unix(self.src_lib, 0)) else: self.src_lib = "" self.tb_file = sim_section.get("tb_file") self.tb_vector = sim_section.get("tb_vector") self.sim_top = sim_section.get("sim_top") if not self.sim_top: self.sim_top = "sim_top" self.src_top_module = sim_section.get("src_top_module") if not self.src_top_module: self.src_top_module = self.sim_top self.uut_name = sim_section.get("uut_name") self.resolution = sim_section.get("resolution") if not self.uut_name: self.uut_name = "UUT" self.sim_time = sim_section.get("sim_time") self.do_msim = sim_section.get("do_msim") self.do_qsim = sim_section.get("do_qsim") self.do_ahdl = sim_section.get("do_asim") self.do_riviera = sim_section.get("do_rsim") _conf = self.flow_options.get("conf") if not self.do_msim: self.do_msim = os.path.join(_conf, "sim", "msim_do.template") if not self.do_qsim: self.do_qsim = os.path.join(_conf, "sim", "qsim_do.template") if not self.do_riviera: self.do_riviera = os.path.join(_conf, "sim", "rsim_do.template") if not self.do_ahdl: if self.pmi: self.do_ahdl = os.path.join(_conf, "sim", "pmi_ahdl.template") else: self.do_ahdl = os.path.join(_conf, "sim", "ahdl_do.template") self.run_modelsim = xTools.get_true(self.flow_options, "run_modelsim") self.run_questasim = xTools.get_true(self.flow_options, "run_questasim") self.run_riviera = xTools.get_true(self.flow_options, "run_riviera") if self.run_modelsim: self.do_template = self.do_msim self.sim_vendor_name = "Modelsim" elif self.run_questasim: self.do_template = self.do_qsim self.sim_vendor_name = "QuestaSim" elif self.run_riviera: self.do_template = self.do_riviera self.sim_vendor_name = "Riviera" else: self.do_template = self.do_ahdl self.sim_vendor_name = "Active" if not os.path.isfile(self.do_template): self.do_template = xTools.get_abs_path(self.do_template, self.src_design) if xTools.not_exists(self.do_template, "DO Template File"): return 1 bali_node = self.final_ldf_dict.get("bali") impl_node = self.final_ldf_dict.get("impl") # ------------- # Fix bugs for getting impl name #<BaliProject version="3.2" title="top" device="LFE5UM-85F-6MG285C" default_implementation="DV100V1"> #<Options/> # <Implementation title="DV100V1" dir="Video" description="Video" synthesis="synplify" default_strategy="Video_timing"> self.impl_name = bali_node.get("default_implementation") self.impl_dir = impl_node.get("dir") if not self.impl_dir: self.impl_dir = self.impl_name # self.project_name = bali_node.get("title") # device = bali_node.get("device") big_version, small_version = xLattice.get_diamond_version() xml_file = os.path.join( _conf, "DiamondDevFile_%s%s.xml" % (big_version, small_version)) self.devkit_parser = xLatticeDev.DevkitParser(xml_file) if self.devkit_parser.process(): return 1 std_devkit = self.devkit_parser.get_std_devkit(device) if not std_devkit: xTools.say_it("Error. Unknown device %s" % device) return 1 family_name = std_devkit.get("family") conf_file = os.path.join(_conf, "sim", "map_lib.ini") if xTools.not_exists(conf_file, "Simulation Library Pairs File"): return 1 sts, raw_lib_dict = xTools.get_conf_options(conf_file) if sts: return 1 my_dict = raw_lib_dict.get("family_map_sim_lib") fam_lower = family_name.lower() map_lib_name = my_dict.get(fam_lower) if not map_lib_name: map_lib_name = fam_lower xTools.say_it("Message: Use map lib name: %s" % fam_lower) if self.dev_lib: map_lib_name = self.dev_lib map_lib_name = re.sub("ovi_", "", map_lib_name) else: if self.run_modelsim or self.run_questasim or self.run_riviera: self.create_dev_lib(map_lib_name) else: self.dev_lib = os.path.join(foundry_path, "..", "active-hdl", "Vlib", "ovi_" + map_lib_name, "ovi_" + map_lib_name + ".lib") self.dev_lib = os.path.abspath(self.dev_lib) # self.pri_lib = "work" self.do_args = dict() self.do_args["sim_top"] = self.sim_top self.do_args["src_top_module"] = self.src_top_module self.do_args["uut_name"] = self.uut_name self.do_args["lib_name"] = "ovi_" + map_lib_name self.do_args["dev_name"] = map_lib_name self.do_args["diamond"] = os.path.dirname( foundry_path ) # On Linux, ENV-KEY FOUNDRY and foundry are different if self.resolution: self.do_args["resolution"] = "-t %s" % self.resolution else: self.do_args["resolution"] = "" if self.sim_time: _sim_time = self.sim_time else: _sim_time = "10 us" self.do_args["sim_time"] = _sim_time
def merge_local_options(self): if self.scuba_type: big_version, small_version = xLattice.get_diamond_version() xml_file = os.path.join( self.conf, "DiamondDevFile_%s%s.xml" % (big_version, small_version)) my_convert = xConvert.ConvertScubaCase(self.src_design, self.devkit, xml_file, self.scuba_type, self.scripts_options) sts = my_convert.process() if sts: return 1 if self.scuba_only: return 1 if self.info_file_name: t = os.path.join(self.src_design, self.info_file_name) if xTools.not_exists(t, "user specified info file"): return 1 info_file = [t] len_info_file = 1 else: info_file = glob.glob(os.path.join(self.src_design, "*.info")) len_info_file = len(info_file) if len_info_file > 1: xTools.say_it("-Error. Found %d info file under %s" % (len_info_file, self.src_design)) return 1 if self.run_ice: if not len_info_file: # read the project file directly ice_prj_files = glob.glob( os.path.join(self.src_design, "par", "*.project")) if not ice_prj_files: ice_prj_files = glob.glob( os.path.join(self.src_design, "synthesis", "*", "*.project")) if not ice_prj_files: ice_prj_files = glob.glob( os.path.join(self.src_design, "project", "*", "*", "*.project")) if xTools.check_file_number(ice_prj_files, "iCEcube2 project file"): return 1 local_options = self.get_ice_project_options(ice_prj_files[0]) self._merge_options(local_options) self.scripts_options["same_ldf_dir"] = os.path.dirname( ice_prj_files[0]) self.scripts_options["use_ice_prj"] = 1 else: sts, info_dict = xTools.get_conf_options(info_file) if sts: return 1 qa_info_dict = info_dict.get("qa") if qa_info_dict: project_file = qa_info_dict.get("project_file") else: project_file = "" if project_file: local_options = self.get_ice_project_options(project_file) self.scripts_options["same_ldf_dir"] = os.path.dirname( project_file) self.scripts_options["use_ice_prj"] = 1 self._merge_options(local_options) else: self.scripts_options["same_ldf_dir"] = os.path.dirname( info_file[0]) self._merge_options(info_dict) else: if not len_info_file: # No info file found ldf_file = glob.glob( os.path.join(self.src_design, "par", "*.ldf")) if not ldf_file: ldf_file = glob.glob(os.path.join(self.src_design, "*.ldf")) if xTools.check_file_number(ldf_file, "Diamond Project File"): return 1 self.scripts_options["ldf_file"] = ldf_file[0] others_path = os.path.join(self.src_design, "others") if os.path.isdir(others_path): self.scripts_options["others_path"] = "./others" else: sts, local_options = xTools.get_conf_options(info_file) if sts: return 1 real_info_file = info_file[0] if xTools.get_fname(real_info_file) == "_qas": new_local_options = qas.get_local_bqs_options( self.conf, local_options, self.src_design) if not new_local_options: xTools.say_it( "-Error. can not get the local info options from _qas.info file" ) return 1 self._merge_options(new_local_options) # self.generate_check_conf_file(real_info_file) else: self._merge_options(local_options) xTools.say_it(self.scripts_options, "Final Options", self.debug)
def get_lib_file(hdl_type, family_path): lib_files = list() p_hdl_type = re.compile("(.+)\Wvhdl\W(\w+)$") if hdl_type == "verilog": for foo in os.listdir(family_path): fext = xTools.get_fext_lower(foo) if fext == ".v": lib_files.append(os.path.join(family_path, foo)) elif fext == ".vhd": xTools.say_it("Warning. found vhd file in %s" % family_path) else: # vhdl mti_path = os.path.join(family_path, "mti") src_path = os.path.join(family_path, "src") list_v, list_vhd = list(), list() m = p_hdl_type.search(family_path) if m: outside_verilog_path = os.path.join(m.group(1), "verilog", m.group(2)) if xTools.not_exists(outside_verilog_path, "Verilog simulation path"): pass else: for v_file in ("GSR.v", "PUR.v"): real_v = os.path.join(outside_verilog_path, v_file) if os.path.isfile(real_v): list_v.append(real_v) pseudo_v = "pseudo_pullup.v" if os.path.isfile(pseudo_v): pass else: xTools.write_file(pseudo_v, v_file_lines) list_v.append(os.path.abspath(pseudo_v)) for foo in os.listdir(src_path): fext = xTools.get_fext_lower(foo) abs_foo = os.path.join(src_path, foo) if fext == ".v": list_v.append(abs_foo) elif fext == ".vhd": list_vhd.append(abs_foo) else: xTools.say_it("Warning. found unknown file %s" % abs_foo) recov = xTools.ChangeDir(mti_path) if sys.platform[:3] == "win": bat_file = "orc_cmpl.bat" else: bat_file = "orc_cmpl.csh" already_have_v = 0 for line in open(bat_file): line = line.strip() if line.startswith("rem"): continue if not line: continue line_list = re.split("\s+", line) if line_list[0] in ("vcom", "vlog"): hdl_file = os.path.abspath(line_list[-1]) if os.path.isfile(hdl_file): lib_files.append(hdl_file) else: if re.search("\*\.v", line_list[-1]): lib_files += list_v already_have_v = 1 else: xTools.say_it("Warning. un-support line: %s" % line) if not already_have_v: lib_files = list_v + lib_files recov.comeback() return lib_files