def _synth(stub: synthesis_service_pb2_grpc.SynthesisServiceStub,
verilog_text: str,
top_module_name: str) -> synthesis_pb2.CompileResponse:
"""Bisects the space of frequencies and sends requests to the server."""
high = FLAGS.max_freq_mhz
low = FLAGS.min_freq_mhz
epsilon = 10
best_result = synthesis_pb2.CompileResponse()
while high - low > epsilon:
current = (high + low) / 2
request = synthesis_pb2.CompileRequest()
request.target_frequency_hz = int(current * 10e6)
request.module_text = verilog_text
request.top_module_name = top_module_name
logging.vlog(3, '--- Request')
logging.vlog(3, request)
response = stub.Compile(request)
if response.slack_ps >= 0:
logging.info('PASS at %dMHz (slack %d).', current,
response.slack_ps)
low = current
if current > best_result.max_frequency_hz:
best_result = response
else:
logging.info('FAIL at %dMHz (slack %d).', current,
response.slack_ps)
high = current
best_result.max_frequency_hz = int(current * 10e6)
return best_result
def test_slack(self):
port, proc = self._start_server(['--max_frequency_ghz=2.0'])
verilog_file = self.create_tempfile(content=VERILOG)
response_text = subprocess.check_output([
CLIENT_PATH, verilog_file.full_path, f'--port={port}', '--ghz=1.0'
]).decode('utf-8')
response = text_format.Parse(response_text,
synthesis_pb2.CompileResponse())
self.assertGreaterEqual(response.slack_ps, 0)
response_text = subprocess.check_output([
CLIENT_PATH, verilog_file.full_path, f'--port={port}', '--ghz=4.0'
]).decode('utf-8')
response = text_format.Parse(response_text,
synthesis_pb2.CompileResponse())
self.assertLess(response.slack_ps, 0)
proc.terminate()
proc.wait()
def test_slack(self):
port, proc = self._start_server()
verilog_file = self.create_tempfile(content=VERILOG)
response_text = subprocess.check_output([
CLIENT_PATH, verilog_file.full_path, f'--port={port}', '--ghz=1.0'
]).decode('utf-8')
response = text_format.Parse(response_text,
synthesis_pb2.CompileResponse())
# The response is generated by parsing testdata/nextpnr.out.
self.assertEqual(response.max_frequency_hz, 180280000)
proc.terminate()
proc.wait()
def test_cell_histogram(self):
port, proc = self._start_server()
verilog_file = self.create_tempfile(content=VERILOG)
response_text = subprocess.check_output([
CLIENT_PATH, verilog_file.full_path, f'--port={port}', '--ghz=1.0'
]).decode('utf-8')
response = text_format.Parse(response_text,
synthesis_pb2.CompileResponse())
# The response is generated by parsing bogusys stdout.
self.assertLen(response.instance_count.cell_histogram, 2)
self.assertIn('CCU2C', response.instance_count.cell_histogram)
self.assertEqual(response.instance_count.cell_histogram['CCU2C'], 32)
self.assertIn('TRELLIS_FF', response.instance_count.cell_histogram)
self.assertEqual(response.instance_count.cell_histogram['TRELLIS_FF'],
192)
proc.terminate()
proc.wait()