def runtest():
resources = xmostest.request_resource("xsim")
speed = 100
build_config = "interfere"
binary = 'i2c_master_async_test/bin/%(config)s/i2c_master_async_test_%(config)s.xe' % {'config':build_config}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = None,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'async_interference_test', {'speed':str(speed)},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size)
checker = SPISlaveChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1F")
tester = xmostest.ComparisonTester(open('slave.expect'),
'lib_spi',
'spi_slave_sim_tests',
'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size),
{'combined': combined, 'burnt_threads': burnt_threads, 'miso_enable': miso_enable, 'mode': mode, 'transfer_size': transfer_size},
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_rx_test(mac, arch, rx_clk, rx_phy, tx_clk, tx_phy, packets, test_file, seed,
level='nightly', extra_tasks=[]):
testname,extension = os.path.splitext(os.path.basename(test_file))
resources = xmostest.request_resource("xsim")
binary = 'test_rx_backpressure/bin/{mac}_{phy}_{arch}/test_rx_backpressure_{mac}_{phy}_{arch}.xe'.format(
mac=mac, phy=tx_phy.get_name(), arch=arch)
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} mac, {phy} phy, {arch} arch sending {n} packets at {clk} (seed {seed})".format(
test=testname, n=len(packets), mac=mac,
phy=tx_phy.get_name(), arch=arch, clk=tx_clk.get_name(), seed=seed)
tx_phy.set_packets(packets)
tester = OutputChecker('lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':tx_phy.get_name(), 'clk':tx_clk.get_name(), 'arch':arch})
tester.set_min_testlevel(level)
simargs = get_sim_args(testname, mac, tx_clk, tx_phy, arch)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy] + extra_tasks,
tester=tester,
simargs=simargs)
def do_input_basic_test(events, timestamps, supply_pin_map, crosstile):
resources = xmostest.request_resource("xsim")
path = ''
if not events and not timestamps and not supply_pin_map and not crosstile:
path += '_basic'
else:
if events:
path += '_events'
if timestamps:
path += '_timestamps'
if supply_pin_map:
path += '_supply_pin_map'
if crosstile:
path += '_crosstile'
binary = 'gpio_input_basic_test/bin/input' + path + \
'/gpio_input_basic_test_input' + path + '.xe'
checker = GPIOBasicChecker(mode="input",
test_port="tile[0]:XS1_PORT_4D",
expected_test_port_data=0b1010,
num_clients=4)
tester = xmostest.ComparisonTester(open('input_basic_test.expected'),
'lib_gpio', 'gpio_sim_tests',
'input_basic_test',
{'events':events,
'timestamps':timestamps,
'supply_pin_map':supply_pin_map,
'crosstile':crosstile},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_slave_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_i2s_callback_sequence/bin/slave_{o}{i}/test_i2s_callback_sequence_slave_{o}{i}.xe'.format(i=num_in, o=num_out)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SSlaveChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
[],
#"tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
[],
#["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
no_start_msg = True)
tester = xmostest.ComparisonTester(open('sequence_check_{o}{i}.expect'.format(i=num_in, o=num_out)),
'lib_i2s', 'i2s_slave_sim_tests',
'sequence_check',
{'ins':num_in, 'outs':num_out},
ignore=['CONFIG:.*'])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
#simargs=['--vcd-tracing', '-o ./test_i2s_callback_sequence/trace.vcd -tile tile[0] -ports'],
tester = tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_tdm_master_test/bin/i2s/i2s_tdm_master_test_i2s.xe'
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_tdm_master_sim_tests',
'i2s_test', {},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
tester = tester)
def do_rx_tx_async(burnt_threads, mosi_enable, speed_tests, combine, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_rx_tx/bin/{burnt}{mosi}{speed}{combined}/spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}'.format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests),
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=[],
timeout=1200,
tester = tester)
def do_rx_tx_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_master_sync_rx_tx/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable),
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def run(arch):
test_name = os.path.splitext(os.path.basename(__file__).replace("test_", "", 1))[0]
resources = xmostest.request_resource("xsim")
binary = '{}/bin/{}/{}_{}.xe'.format(test_name, arch, test_name, arch)
tester = xmostest.ComparisonTester(open('{}.expect'.format(test_name)),
'lib_xcore_c', 'xcore_c_tests',
"{}_{}".format(test_name, arch), regexp=True)
tester.set_min_testlevel("smoke")
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[],
tester=tester,
simargs=['--xscope', '-offline xscope.xmt'],
loopback=[{'from': 'tile[0]:XS1_PORT_1A',
'to': 'tile[0]:XS1_PORT_1C'},
{'from': 'tile[0]:XS1_PORT_1B',
'to': 'tile[0]:XS1_PORT_1D'},
{'from': 'tile[1]:XS1_PORT_1A',
'to': 'tile[1]:XS1_PORT_1C'},
{'from': 'tile[1]:XS1_PORT_1B',
'to': 'tile[1]:XS1_PORT_1D'}])
def do_multi_device_async(burnt_threads, mosi_enable):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_multi_device/bin/{burnt}{mosi}/spi_master_async_multi_device_{burnt}{mosi}.xe".format(burnt=burnt_threads,mosi=mosi_enable)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_async_multi_device_{burnt}{mosi}'.format(burnt=burnt_threads, mosi=mosi_enable),
regexp=True)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=['--vcd-tracing', '-o ./spi_master_async_multi_device/trace.vcd -tile tile[0] -pads -functions'],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_dc_offset_removal_test(testlevel):
# Check if the test is running in an environment with hardware resources
# available - the test takes a long time to run in the simulator
args = xmostest.getargs()
if not args.remote_resourcer:
# Abort the test
print 'remote resourcer not avaliable'
return
binary = 'test_dc_offset_removal/bin/test_dc_offset_removal.xe'
tester = xmostest.ComparisonTester(open('test_dc_offset_removal.expect'),
'lib_mic_array',
'lib_mic_array_backend_tests',
'dc_offset_removal_test_%s'%testlevel)
tester.set_min_testlevel(testlevel)
resources = xmostest.request_resource("testrig_os_x_12",
tester)
run_job = xmostest.run_on_xcore(resources['uac2_xcore200_mc_analysis_device_1'],
binary,
tester=tester)
xmostest.complete_all_jobs()
def do_test(arch):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/%(arch)s/i2c_master_reg_test_%(arch)s.xe' % {
'arch' : arch
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff, 0x05, 0x11, 0x22],
expected_speed=400,
ack_sequence=[False, # NACK header
True, True, False, # NACK before data
True, False, # NACK before data
True, False, # NACK before data
False, # NACK address
True, False, # NACK before data
True, False, # NACK before data
True, True, False # NACK before data
])
tester = xmostest.ComparisonTester(open('reg_ops_nack.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'reg_ops_nack_test',
{'arch' : arch},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/i2c_master_reg_test.xe'
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff, 0x05],
expected_speed = 400,
ack_sequence=[True, True, False,
True, True, True, False,
True, True, True, True, False,
True, True,
True, True, True,
True, True, True, True])
tester = xmostest.ComparisonTester(open('reg_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'reg_ops_test',
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(baud):
myenv = {'baud': baud}
resources = xmostest.request_resource("xsim")
rx_checker = UARTRxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
RxParity['UART_PARITY_NONE'], baud, 1, 8)
tx_checker = UARTTxChecker("tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1C",
TxParity['UART_PARITY_NONE'], baud, 4, 1, 8)
tester = xmostest.ComparisonTester(open('test_loopback_uart.expect'),
"lib_uart", "sim_regression", "loopback", myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_loopback/bin/{}/app_uart_test_loopback_{}.xe'.format(baud, baud),
simthreads=[rx_checker, tx_checker],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -functions -ports -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_master_test(speed, comb):
resources = xmostest.request_resource("xsim")
if comb:
build_config = "comb_%d" % speed
config = {'speed':speed,'impl':'comb'}
else:
build_config = str(speed)
config = {'speed':speed,'impl':'noncomb'}
binary = 'i2c_master_async_test/bin/%(config)s/i2c_master_async_test_%(config)s.xe' % {'config':build_config}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = speed,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'async_basic_test', config,
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(mac, rx_clk, rx_phy, tx_clk, tx_phy):
start_test(rx_phy)
resources = xmostest.request_resource("xsim")
testname = 'test_time_tx'
level = 'nightly'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=rx_phy.get_name())
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} {phy} phy at {clk}".format(
test=testname, mac=mac, phy=rx_phy.get_name(), clk=rx_clk.get_name())
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{mac}_{phy}_{clk}.expect'.format(
folder=expect_folder, test=testname, mac=mac, phy=rx_phy.get_name(), clk=rx_clk.get_name())
create_expect(expect_filename)
tester = xmostest.ComparisonTester(open(expect_filename),
'lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':rx_phy.get_name(), 'clk':rx_clk.get_name()},
regexp=True)
tester.set_min_testlevel('nightly')
simargs = get_sim_args(testname, mac, rx_clk, rx_phy)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_input_events_test(events):
resources = xmostest.request_resource("xsim")
path = ''
if not events:
path += '_basic'
else:
if events:
path += '_events'
binary = 'gpio_input_events_test/bin/input' + path + \
'/gpio_input_events_test_input' + path + '.xe'
checker = GPIOEventsChecker(test_port="tile[0]:XS1_PORT_4D",
expected_test_port_data=0b1010,
num_clients=4,
trigger_port="tile[0]:XS1_PORT_4B")
tester = xmostest.ComparisonTester(open('input_events_test%s.expected' % path),
'lib_gpio', 'gpio_sim_tests',
'input_events_test',
{'events':events},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_test(baud):
myenv = {'baud': baud}
path = "app_uart_test_multi_rx"
resources = xmostest.request_resource("xsim")
rx_checker = UARTRxChecker("tile[0]:XS1_PORT_8B.0", "tile[0]:XS1_PORT_1A", RxParity['UART_PARITY_NONE'], baud, 1, 8, data=[0x7f, 0x00, 0x2f, 0xff])
rx_checker2 = UARTRxChecker("tile[0]:XS1_PORT_8B.2", "tile[0]:XS1_PORT_1A", RxParity['UART_PARITY_NONE'], baud/2, 1, 8, data=[0xaa, 0x01, 0xfc, 0x8e])
uart_clock = UARTClockDevice("tile[0]:XS1_PORT_1L", 1843200)
drive_high0 = DriveHigh("tile[0]:XS1_PORT_8B.1")
tester = xmostest.ComparisonTester(open('test_rx_multi_uart.expect'),
"lib_uart", "sim_regression", "multi_rx_simple", myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_multi_rx/bin/smoke/app_uart_test_multi_rx_smoke.xe',
simthreads=[drive_high0, rx_checker, rx_checker2, uart_clock],
xscope_io=True,
tester=tester,
simargs=["--trace-to", "trace", "--vcd-tracing", "-tile tile[0] -pads -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_master_test/bin/{tl}_{i}{o}/i2s_master_test_{tl}_{i}{o}.xe'.format(i=num_in, o=num_out,tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_master_sim_tests',
'basic_test_%s'%testlevel, {'num_in':num_in, 'num_out':num_out},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
simargs=[],
suppress_multidrive_messages = True,
tester = tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_frame_master_test/bin/{tl}_{i}{o}/i2s_frame_master_test_{tl}_{i}{o}.xe'.format(i=num_in, o=num_out,tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
False) # Don't check the bclk stops precisely as the hardware can't do that
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_frame_master_sim_tests',
'basic_test_%s'%testlevel, {'num_in':num_in, 'num_out':num_out},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
simargs=[],
# simargs=['--trace-to', 'sim.log', '--vcd-tracing', '-o ./i2s_frame_master_test/trace.vcd -tile tile[0] -ports-detailed -functions'],
suppress_multidrive_messages = True,
tester = tester)
def do_sp_test(stop, speed):
resources = xmostest.request_resource("xsim")
binary = 'i2c_sp_test/bin/%(speed)d_%(stop)s/i2c_sp_test_%(speed)d_%(stop)s.xe' % {
'speed' : speed,
'stop' : stop
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_8A.1",
"tile[0]:XS1_PORT_8A.3",
tx_data=[0x99, 0x3a, 0xff, 0xaa, 0xbb],
expected_speed=speed,
# Test some sequences ending with ACK, some with NACK
ack_sequence=[True, True, False,
True, True, True, False])
tester = xmostest.ComparisonTester(open('single_port_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'single_port_test',
{'speed':speed, 'stop':stop},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
sim_args = ['--weak-external-drive']
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=sim_args,
suppress_multidrive_messages = True,
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'i2s_tdm_master_test/bin/tdm/i2s_tdm_master_test_tdm.xe'
checker = TDMMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1N",
["tile[0]:XS1_PORT_1O"],
["tile[0]:XS1_PORT_1P"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
extra_clocks = 16)
tester = xmostest.ComparisonTester(open('tdm_cb_test.expect'),
'lib_i2s', 'i2s_tdm_master_sim_tests',
'tdm_test',
{},
regexp=True,
ignore=["CONFIG:"])
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
tester = tester,
simargs = ['--vcd-tracing','-o ttt.vcd -tile tile[0] -ports'])
return
def do_master_test(arch, speed, impl, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_async_test/bin/%(impl)s_%(speed)s_%(arch)s_%(stop)s/i2c_master_async_test_%(impl)s_%(speed)s_%(arch)s_%(stop)s.xe' % {
'impl' : impl,
'speed' : speed,
'arch' : arch,
'stop' : stop
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = speed,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'async_basic_test',
{'speed' : speed, 'impl' : impl, 'arch' : arch, 'stop' : stop},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_backend_test(length, frame_count, testlevel):
# Check if the test is running in an environment with hardware resources
# available - the test takes a long time to run in the simulator
args = xmostest.getargs()
if not args.remote_resourcer:
# Abort the test
print 'remote resourcer not avaliable'
return
binary = 'test_fir_model/bin/COUNT{fc}_{len}/test_fir_model_COUNT{fc}_{len}.xe'.format(fc=frame_count, len=length)
tester = xmostest.ComparisonTester(open('fir_model.expect'),
'lib_mic_array',
'lib_mic_array_backend_tests',
'backend_test_%s'%testlevel,
{'frame_count':frame_count, 'length':length})
tester.set_min_testlevel(testlevel)
resources = xmostest.request_resource("testrig_os_x_12",
tester)
run_job = xmostest.run_on_xcore(resources['uac2_xcore200_mc_analysis_device_1'],
binary,
tester=tester, timeout=3600)
xmostest.complete_all_jobs()
def do_input_1bit_basic_test(timestamps):
resources = xmostest.request_resource("xsim")
path = ''
if not timestamps:
path += '_basic'
else:
if timestamps:
path += '_timestamps'
binary = 'gpio_input_1bit_test/bin/input' + path + \
'/gpio_input_1bit_test_input' + path + '.xe'
checker = GPIOBasicChecker(mode="input",
test_port="tile[0]:XS1_PORT_1A",
expected_test_port_data=0b1,
num_clients=1)
tester = xmostest.ComparisonTester(open('input_1bit_basic_test.expected'),
'lib_gpio', 'gpio_sim_tests',
'input_1bit_basic_test',
{'timestamps':timestamps,},
regexp=False)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'lcd_testbench_port16/bin/lcd_testbench.xe'
checker = LCD_syncTiming_checker("tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1I",
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_1J",
"tile[0]:XS1_PORT_1K",
lcd_h_front_porch = 5,
lcd_h_back_porch = 40,
lcd_h_pulse_width = 1,
lcd_v_front_porch = 8,
lcd_v_back_porch = 8,
lcd_v_pulse_width = 1,
lcd_clk_div = 4,
lcd_height = 272,
lcd_width = 480)
tester = xmostest.ComparisonTester(open('lcd_syncTiming_test.expect'),
'lib_lcd', 'lcd_sim_tests',
'sync_test', regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'tdm_master_cb_test/bin/{t}_{i}{o}/tdm_master_cb_test_{t}_{i}{o}.xe'.format(i=num_in, o=num_out, t = testlevel)
checker = TDMMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M")
tester = xmostest.ComparisonTester(open('tdm_cb_test.expect'),
'lib_i2s', 'tdm_master_sim_tests',
'basic_test_%s'%testlevel,
{'num_in':num_in, 'num_out':num_out},
regexp=True,
ignore=["CONFIG:"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=[],
simargs=['--vcd-tracing', '-o ./tdm_master_cb_test/trace.vcd -tile tile[0] -ports-detailed'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(mac, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_etype_filter'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=tx_phy.get_name())
print "Running {test}: {phy} phy at {clk}".format(
test=testname, phy=tx_phy.get_name(), clk=tx_clk.get_name())
rand = random.Random()
dut_mac_address = get_dut_mac_address()
packets = [
MiiPacket(rand, dst_mac_addr=dut_mac_address, src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x11, 0x11], data_bytes=[1,2,3,4] + [0 for x in range(50)]),
MiiPacket(rand, dst_mac_addr=dut_mac_address, src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x22, 0x22], data_bytes=[5,6,7,8] + [0 for x in range(60)])
]
tx_phy.set_packets(packets)
tester = xmostest.ComparisonTester(open('test_etype_filter.expect'),
'lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':tx_phy.get_name(), 'clk':tx_clk.get_name()})
simargs = get_sim_args(testname, mac, tx_clk, tx_phy)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_slave_test(speed, level):
resources = xmostest.request_resource("xsim")
binary = 'i2c_slave_test/bin/i2c_slave_test.xe'
checker = I2CSlaveChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tsequence =
[("w", 0x3c, [0x33, 0x44, 0x3]),
("r", 0x3c, 3),
("w", 0x3c, [0x99]),
("w", 0x44, [0x33]),
("r", 0x3c, 1),
("w", 0x3c, [0x22, 0xff])],
speed = speed)
tester = xmostest.ComparisonTester(open('basic_slave_test.expect'),
'lib_i2c', 'i2c_slave_sim_tests',
'basic_test', {'speed':speed},
regexp=True)
tester.set_min_testlevel(level)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_master_test(arch, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_test/bin/tx_only_%(stop)s_%(arch)s/i2c_master_test_tx_only_%(stop)s_%(arch)s.xe' % {
'stop' : stop,
'arch' : arch,
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = 400,
ack_sequence=[True, True, True,
True, True, False,
False, True])
tester = xmostest.ComparisonTester(open('ack_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'ack_test',
{'speed':400, 'arch' : arch, 'stop' : stop},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
tester = xmostest.ComparisonTester(open('complex_fir_test.expect'),
'lib_dsp', 'simple_tests',
'app_complex_fir', {})
xmostest.run_on_simulator(resources['xsim'],
'../AN00209_xCORE-200_DSP_Library/app_complex_fir/bin/app_complex_fir.xe',
tester=tester, timeout=1200)
def runtest():
resources = xmostest.request_resource("xsim")
tester = xmostest.ComparisonTester(open('design_test.expect'),
'lib_dsp', 'simple_tests',
'app_design', {})
xmostest.run_on_simulator(resources['xsim'],
'../AN00209_xCORE-200_DSP_Library/app_design/bin/app_design.xe',
tester=tester)
def runtest():
resources = xmostest.request_resource("xsim")
tester = xmostest.ComparisonTester(open('os3_test.expect'), 'lib_src',
'fixed_factor_of_3_tests', 'app_os3',
{})
xmostest.run_on_simulator(resources['xsim'],
'../examples/app_os3/bin/app_os3.xe',
tester=tester)
def runtest():
test_name = "assert_test_unit"
resources = xmostest.request_resource("xsim")
tester = xmostest.ComparisonTester(open(test_name + '.expect'),
'lib_xassert', 'simple_tests',
test_name, {})
xmostest.run_on_simulator(resources['xsim'],
test_name + '/bin/' + test_name + '.xe',
tester=tester)
def do_ssrc_test_iteration(input_sr, output_sr, testlevel):
simargs_ssrc = ""
resources = xmostest.request_resource("xsim")
file_name = file_name_builder()
#print ('Running SSRC test iteration SR input = %d, output = %d' % (input_sr, output_sr))
test_files = (os.path.join(
"src_output", file_name.output_signal(input_sr, output_sr,
"pure_sine")),
os.path.join(
"src_output",
file_name.output_signal(input_sr, output_sr,
"inter_modulation")))
golden_files = (os.path.join(
"ssrc_test", "expected",
file_name.golden_signal(input_sr, output_sr, "pure_sine")),
os.path.join(
"ssrc_test", "expected",
file_name.golden_signal(input_sr, output_sr,
"inter_modulation")))
tester = FileComparisonTester(test_files,
golden_files,
"lib_src",
"ssrc_test",
str(input_sr) + "->" + str(output_sr), {},
regexp=False,
ignore=[])
tester.set_min_testlevel(testlevel)
args = [
"-i",
os.path.join("src_input", file_name.test_signal(input_sr,
"pure_sine")),
os.path.join("src_input",
file_name.test_signal(input_sr, "inter_modulation")),
"-o", test_files[0], test_files[1]
]
args += [
"-f",
str(input_sr), "-g",
str(output_sr), "-n",
str(num_in_samps)
]
appargs_ssrc = args
#print("xsim cmd line = %s" % " ".join(appargs_ssrc))
xmostest.run_on_simulator(resources["xsim"],
os.path.join("ssrc_test", "bin", "ssrc_test.xe"),
appargs=appargs_ssrc,
simargs=simargs_ssrc,
tester=tester)
xmostest.complete_all_jobs()
"""Uncomment this line to help debug - ensures that previous test run before next iteration loop. Makes reading stdout easier"""
def runtest():
testlevel = 'smoke'
resources = xmostest.request_resource('xsim')
binary = 'xscope_device/bin/xscope_device.xe'.format()
tester = xmostest.ComparisonTester(open('xscope_device.expect'),
'lib_device_control',
'lib_device_control_tests',
'xscope_device_api',
{})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary, simargs=[], tester=tester)
def do_rx_test(arch,
tx_clk,
tx_phy,
packets,
test_file,
seed,
level='nightly',
extra_tasks=[]):
""" Shared test code for all RX tests using the test_rx application.
"""
testname, extension = os.path.splitext(os.path.basename(test_file))
resources = xmostest.request_resource("xsim")
binary = '{testname}/bin/{arch}/{testname}_{arch}.xe'.format(
testname=testname, arch=arch)
print binary
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {arch} arch sending {n} packets at {clk} (seed {seed})".format(
test=testname,
n=len(packets),
arch=arch,
clk=tx_clk.get_name(),
seed=seed)
tx_phy.set_packets(packets)
#rx_phy.set_expected_packets(packets)
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{arch}.expect'.format(
folder=expect_folder,
test=testname,
phy=tx_phy.get_name(),
clk=tx_clk.get_name(),
arch=arch)
create_expect(packets, expect_filename)
tester = xmostest.ComparisonTester(open(expect_filename), 'lib_xud',
'xud_sim_tests', testname, {
'clk': tx_clk.get_name(),
'arch': arch
})
tester.set_min_testlevel(level)
simargs = get_sim_args(testname, tx_clk, tx_phy, arch)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[tx_clk, tx_phy] + extra_tasks,
tester=tester,
simargs=simargs)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'test_i2s_callback_sequence/bin/i2s_tdm_i2s/test_i2s_callback_sequence_i2s_tdm_i2s.xe'
tester = xmostest.ComparisonTester(open('sequence_check_44.expect'),
'lib_i2s', 'i2s_tdm_master_sim_tests',
'sequence_check_i2s',
{})
xmostest.run_on_simulator(resources['xsim'], binary,
tester = tester)
def runtest():
testlevel = 'smoke'
resources = xmostest.request_resource('xsim')
binary = 'dbc_timestamp_valid/bin/dbc_timestamp_valid.xe'.format()
tester = xmostest.ComparisonTester(open('dbc_timestamp_valid.expect'),
'lib_tsn', 'lib_tsn_tests',
'dbc_timestamp_valid', {})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'],
binary,
simargs=[],
tester=tester)
def do_slave_test(lock_type):
resources = xmostest.request_resource("xsim")
binary = 'locks_test/bin/{}/locks_test_{}.xe'.format(lock_type, lock_type)
tester = xmostest.ComparisonTester(open('locks.expect'),
'lib_locks', 'locks_sim_tests',
'locks_test', {'lock_type' : lock_type})
tester.set_min_testlevel('smoke')
xmostest.run_on_simulator(resources['xsim'], binary,
simargs=['--xscope', '-offline xscope.xmt'],
tester = tester)
def do_test(testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_lib_include/bin/test_lib_include.xe'
tester = xmostest.ComparisonTester(open('test_lib_include.expect'),
'lib_mic_array',
'lib_mic_array_backend_tests',
'lib_include_test_%s' % testlevel)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary, tester=tester)
def runtest():
testlevel = 'smoke'
resources = xmostest.request_resource('xsim')
binary = 'i2c_end_to_end_sim/bin/i2c_end_to_end_sim.xe'.format()
tester = xmostest.ComparisonTester(open('i2c_end_to_end_sim.expect'),
'lib_device_control',
'lib_device_control_tests',
'i2c_end_to_end',
{})
tester.set_min_testlevel(testlevel)
simargs = ("--plugin", "LoopbackPort.dll", "-pullup -port tile[0] XS1_PORT_1A 1 0 -port tile[1] XS1_PORT_1A 1 0 ",
"--plugin", "LoopbackPort.dll", "-pullup -port tile[0] XS1_PORT_1B 1 0 -port tile[1] XS1_PORT_1B 1 0 ",
"--trace-to", "/dev/null") #This extra argument has been added to redirect the warnings about pin driving from stdout
xmostest.run_on_simulator(resources['xsim'], binary, simargs=simargs, tester=tester)
def do_test(num_in, num_out, chans_per_frame, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_i2s_callback_sequence/bin/tdm_{o}{i}{C}/test_i2s_callback_sequence_tdm_{o}{i}{C}.xe'.format(i=num_in, o=num_out, C=chans_per_frame)
tester = xmostest.ComparisonTester(open('tdm_sequence_check_{o}{i}{C}.expect'.format(i=num_in, o=num_out, C=chans_per_frame)),
'lib_i2s', 'tdm_master_sim_tests',
'sequence_check',
{'ins':num_in, 'outs':num_out, 'chans_per_frame':chans_per_frame})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
tester = tester)
def test_dual_lcd():
resources = xmostest.request_resource("LCD_test_setup")
xmostest.build('dual_lcd_testbench')
print "\nRunning on A16 board with LCD slices connected to circle and square slots"
print "\nPlease check LCD displays for fading Red, Green and Blue bars bounded by a white box"
print "\nPress CTRL-c to quit\n"
binary = 'dual_lcd_testbench/bin/dual_lcd_testbench.xe'
xmostest.run_on_xcore(resources['A16'], binary,
tester = None,
enable_xscope = False,
xscope_handler = None,
timeout = 600)
def do_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_i2s_callback_sequence/bin/master_{o}{i}/test_i2s_callback_sequence_master_{o}{i}.xe'.format(
i=num_in, o=num_out)
tester = xmostest.ComparisonTester(
open('sequence_check_{o}{i}.expect'.format(i=num_in, o=num_out)),
'lib_i2s', 'i2s_master_sim_tests', 'sequence_check', {
'ins': num_in,
'outs': num_out
})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary, tester=tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'read_write_testbench/bin/read_write_testbench.xe'
tester = xmostest.ComparisonTester(open('read_write_test.expect'),
'lib_display_controller', 'functionality_tests',
'read_write_test', regexp=True)
# tester.set_min_testlevel('smoke')
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def run(arch):
test_name = os.path.splitext(os.path.basename(__file__).replace("test_", "", 1))[0]
resources = xmostest.request_resource("xsim")
binary = '{}/bin/{}/{}_{}.xe'.format(test_name, arch, test_name, arch)
tester = xmostest.ComparisonTester(open('{}.expect'.format(test_name)),
'lib_trycatch', 'trycatch_tests',
"{}_{}".format(test_name, arch))
tester.set_min_testlevel("smoke")
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[],
tester=tester,
simargs=['--xscope', '-offline xscope.xmt'])
def do_channel_ordering_test(test_name, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_channel_ordering/bin/{t}/test_channel_ordering_{t}.xe'.format(t=test_name)
tester = xmostest.ComparisonTester(open('test_channel_ordering_{t}.expect'.format(t=test_name)),
'lib_mic_array',
'lib_mic_array_channel_ordering_tests',
'channel_ordering_test_%s'%testlevel,
{'config':test_name})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simargs=["--plugin", "LoopbackPort.dll", "-port tile[0] XS1_PORT_8A 8 0 -port tile[0] XS1_PORT_8B 8 0 "],
tester = tester)
def do_test(mac, rx_clk, rx_phy, tx_clk, tx_phy):
start_test(rx_phy)
resources = xmostest.request_resource("xsim")
testname = 'test_time_tx'
level = 'nightly'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=rx_phy.get_name())
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} {phy} phy at {clk}".format(
test=testname,
mac=mac,
phy=rx_phy.get_name(),
clk=rx_clk.get_name())
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{mac}_{phy}_{clk}.expect'.format(
folder=expect_folder,
test=testname,
mac=mac,
phy=rx_phy.get_name(),
clk=rx_clk.get_name())
create_expect(expect_filename)
tester = xmostest.ComparisonTester(open(expect_filename),
'lib_ethernet',
'basic_tests',
testname, {
'mac': mac,
'phy': rx_phy.get_name(),
'clk': rx_clk.get_name()
},
regexp=True)
tester.set_min_testlevel('nightly')
simargs = get_sim_args(testname, mac, rx_clk, rx_phy)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size,
testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(
com=combined,
burnt=burnt_threads,
miso=miso_enable,
m=mode,
t=transfer_size)
checker = SPISlaveChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1F")
tester = xmostest.ComparisonTester(
open('slave.expect'),
'lib_spi',
'spi_slave_sim_tests',
'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,
burnt=burnt_threads,
miso=miso_enable,
m=mode,
t=transfer_size),
{
'combined': combined,
'burnt_threads': burnt_threads,
'miso_enable': miso_enable,
'mode': mode,
'transfer_size': transfer_size
},
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(
resources['xsim'],
binary,
simthreads=[checker],
#simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'],
simargs=[],
suppress_multidrive_messages=False,
tester=tester)
def do_test(arch, stop):
resources = xmostest.request_resource("xsim")
speed = 400
binary = 'i2c_master_test/bin/rx_tx_%(speed)s_%(stop)s_%(arch)s/i2c_master_test_rx_tx_%(speed)s_%(stop)s_%(arch)s.xe' % {
'speed': speed,
'stop': stop,
'arch': arch,
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff],
expected_speed=170,
clock_stretch=5000,
ack_sequence=[
True, True, False, True, True, True, True,
True, False, True, False
])
tester = xmostest.ComparisonTester(open('master_test_%s.expect' % stop),
'lib_i2c',
'i2c_master_sim_tests',
'clock_stretch', {
'speed': speed,
'stop': stop,
'arch': arch
},
regexp=True)
# vcd_args = '-o test.vcd'
# vcd_args += ( ' -tile tile[0] -ports -ports-detailed -instructions'
# ' -functions -cycles -clock-blocks -pads' )
# sim_args = ['--weak-external-drive', '--trace-to', 'sim.log']
# sim_args += [ '--vcd-tracing', vcd_args ]
sim_args = ['--weak-external-drive']
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=sim_args,
suppress_multidrive_messages=True,
tester=tester)
def do_test(baud):
myenv = {'baud': baud}
path = "app_uart_test_multi_rx"
resources = xmostest.request_resource("xsim")
rx_checker = UARTRxChecker("tile[0]:XS1_PORT_8B.0",
"tile[0]:XS1_PORT_1A",
RxParity['UART_PARITY_NONE'],
baud,
1,
8,
data=[0x7f, 0x00, 0x2f, 0xff])
rx_checker2 = UARTRxChecker("tile[0]:XS1_PORT_8B.2",
"tile[0]:XS1_PORT_1A",
RxParity['UART_PARITY_NONE'],
baud / 2,
1,
8,
data=[0xaa, 0x01, 0xfc, 0x8e])
uart_clock = UARTClockDevice("tile[0]:XS1_PORT_1L", 1843200)
drive_high0 = DriveHigh("tile[0]:XS1_PORT_8B.1")
tester = xmostest.ComparisonTester(open('test_rx_multi_uart.expect'),
"lib_uart",
"sim_regression",
"multi_rx_simple",
myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_multi_rx/bin/smoke/app_uart_test_multi_rx_smoke.xe',
simthreads=[drive_high0, rx_checker, rx_checker2, uart_clock],
xscope_io=True,
tester=tester,
simargs=[
"--trace-to", "trace", "--vcd-tracing",
"-tile tile[0] -pads -o trace.vcd"
],
clean_before_build=True,
build_env=myenv)
def do_test(mac, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_etype_filter'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=tx_phy.get_name())
print "Running {test}: {phy} phy at {clk}".format(test=testname,
phy=tx_phy.get_name(),
clk=tx_clk.get_name())
rand = random.Random()
dut_mac_address = get_dut_mac_address()
packets = [
MiiPacket(rand,
dst_mac_addr=dut_mac_address,
src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x11, 0x11],
data_bytes=[1, 2, 3, 4] + [0 for x in range(50)]),
MiiPacket(rand,
dst_mac_addr=dut_mac_address,
src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x22, 0x22],
data_bytes=[5, 6, 7, 8] + [0 for x in range(60)])
]
tx_phy.set_packets(packets)
tester = xmostest.ComparisonTester(open('test_etype_filter.expect'),
'lib_ethernet', 'basic_tests', testname,
{
'mac': mac,
'phy': tx_phy.get_name(),
'clk': tx_clk.get_name()
})
simargs = get_sim_args(testname, mac, tx_clk, tx_phy)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_frontend_test(channel_count, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_pdm_interface/bin/CH{ch}/test_pdm_interface_CH{ch}.xe'.format(
ch=channel_count)
tester = xmostest.ComparisonTester(open('pdm_interface.expect'),
'lib_mic_array',
'lib_mic_array_frontend_tests',
'frontend_test_%s' % testlevel,
{'channel_count': channel_count})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'],
binary,
simargs=[],
tester=tester)
def do_test(arch):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/%(arch)s/i2c_master_reg_test_%(arch)s.xe' % {
'arch': arch
}
checker = I2CMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff, 0x05, 0x11, 0x22],
expected_speed=400,
ack_sequence=[
False, # NACK header
True,
True,
False, # NACK before data
True,
False, # NACK before data
True,
False, # NACK before data
False, # NACK address
True,
False, # NACK before data
True,
False, # NACK before data
True,
True,
False # NACK before data
])
tester = xmostest.ComparisonTester(open('reg_ops_nack.expect'),
'lib_i2c',
'i2c_master_sim_tests',
'reg_ops_nack_test', {'arch': arch},
regexp=True)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_slave_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_slave_test/bin/{tl}_{i}{o}_inv/i2s_slave_test_{tl}_{i}{o}_inv.xe'.format(
i=num_in, o=num_out, tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SSlaveChecker("tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C", [
"tile[0]:XS1_PORT_1H", "tile[0]:XS1_PORT_1I",
"tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"
], [
"tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"
],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
invert_bclk=True)
tester = xmostest.ComparisonTester(open('bclk_invert.expect'),
'lib_i2s',
'i2s_slave_sim_tests',
'slave_bclk_invert_%s' % testlevel, {
'num_in': num_in,
'num_out': num_out
},
regexp=True,
ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(
resources['xsim'],
binary,
simthreads=[clk, checker],
#simargs=['--vcd-tracing', '-o ./i2s_slave_test/trace.vcd -tile tile[0] -ports-detailed'],
suppress_multidrive_messages=True,
tester=tester)
def do_input_1bit_events_test():
resources = xmostest.request_resource("xsim")
binary = 'gpio_input_1bit_test/bin/input_events/gpio_input_1bit_test_input_events.xe'
checker = GPIOEventsChecker(test_port="tile[0]:XS1_PORT_1A",
expected_test_port_data=0b1,
num_clients=1,
trigger_port="tile[0]:XS1_PORT_4B")
tester = xmostest.ComparisonTester(open('input_1bit_events_test.expected'),
'lib_gpio',
'gpio_sim_tests',
'input_1bit_events_test',
regexp=False)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
tester=tester)
def do_test(baud):
myenv = {'baud': baud}
path = "app_uart_test_rx"
resources = xmostest.request_resource("xsim")
checker = UARTRxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B", Parity['UART_PARITY_NONE'], baud, 1, 8)
tester = xmostest.ComparisonTester(open('test_rx_uart.expect'),
"lib_uart", "sim_regression", "rx", myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_rx/bin/smoke/app_uart_test_rx_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -ports -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_test(baud, parity, bpb):
myenv = {'parity': parity, 'baud': baud, 'bits_per_byte': bpb}
path = "app_uart_test_bpb"
resources = xmostest.request_resource("xsim")
checker = UARTTxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B", Parity[parity], baud, 4, 1, bpb)
tester = xmostest.ComparisonTester(open('test_tx_bpb_uart.expect'),
"lib_uart", "sim_regression", "tx_bpb", myenv,
regexp=True)
# Only want even parity @ 115200 baud for smoke tests
if baud != 115200 or parity != 'UART_PARITY_EVEN':
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_bpb/bin/smoke/app_uart_test_bpb_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
clean_before_build=True,
build_env=myenv)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'i2c_test_repeated_start/bin/i2c_test_repeated_start.xe'
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
expected_speed=400)
tester = xmostest.ComparisonTester(open('repeated_start.expect'),
'lib_i2c',
'i2c_master_sim_tests',
'repeated_start',
regexp=True)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
