def create_system(self): system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, SimpleDDR3, None, False) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True self.init_system(system) return system
def create_system(self): system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, None, False) # We typically want the simulator to panic if the kernel # panics or oopses. This prevents the simulator from running # an obviously failed test case until the end of time. system.panic_on_panic = True system.panic_on_oops = True self.init_system(system) return system
# I/O Cache # --------------------- class IOCache(BaseCache): assoc = 8 block_size = 64 latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 addr_ranges = [AddrRange(0, size='256MB')] forward_snoops = False #cpu cpu = DerivO3CPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the l1/l2 bus system.toL2Bus = CoherentBus() system.iocache = IOCache() system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s
class IOCache(BaseCache): assoc = 8 block_size = 64 hit_latency = '50ns' response_latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 addr_ranges = [AddrRange(0, size='256MB')] forward_snoops = False #cpu cpu = TimingSimpleCPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the l1/l2 bus system.toL2Bus = CoherentBus() system.iocache = IOCache() system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size='32kB', assoc=1), L1(size='32kB', assoc=4))
class IOCache(BaseCache): assoc = 8 block_size = 64 hit_latency = '50ns' response_latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 addr_ranges = [AddrRange(0, size='256MB')] forward_snoops = False #cpu cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2)] #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.iocache = IOCache() system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus system.toL2Bus = CoherentBus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus:
# I/O Cache # --------------------- class IOCache(BaseCache): assoc = 8 block_size = 64 latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 addr_range=AddrRange(0, size='256MB') forward_snoops = False #cpu cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port system.cpu = cpus #create the l1/l2 bus system.toL2Bus = Bus() #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port system.l2c.num_cpus = 2
def create_system(self): system = FSConfig.makeArmSystem(self.mem_mode, self.machine_type, None, False) self.init_system(system) return system