def i_ASN(): global PC if AC != 0: PC = (PC + 1) & WORDMASK Trace.itrace('ASN') return 1
def i_HSN(): global PC if not Ptr.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('HSN') return 1
def i_SSN(): global PC if not Display.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('SSN') return 1
def i_ASM(): global PC if (AC & HIGHBITMASK): PC = (PC + 1) & WORDMASK Trace.itrace('ASM') return 1
def i_PSF(indirect, address, instruction): global PC if Ptp.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('PSF') return 1
def i_TSN(): global PC if not TtyOut.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('TSN') return 1
def i_RRC(indirect, address, instruction): global AC AC |= TtyIn.read() TtyIn.clear() Trace.itrace('RRC') return 1
def i_KRC(indirect, address, instruction): global AC AC |= Kbd.read() Kbd.clear() Trace.itrace('KRC') return 1
def i_SSF(): global PC if Display.ready(): # skip if 40Hz sync on PC = (PC + 1) & WORDMASK Trace.itrace('SSF') return 1
def i_TSF(): global PC if TtyOut.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('TSF') return 1
def i_SAR1(indirect, address, instruction): global AC high_bit = AC & HIGHBITMASK AC = (AC >> 1) | high_bit Trace.itrace('SAR', False, 1) return 1
def i_KSN(): global PC if not Kbd.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('KSN') return 1
def i_DSN(): global PC if not DisplayCPU.ison(): PC = (PC + 1) & WORDMASK Trace.itrace('DSN') return 1
def i_KSF(): global PC if Kbd.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('KSF') return 1
def i_LSZ(): global PC if L == 0: PC = (PC + 1) & WORDMASK Trace.itrace('LSZ') return 1
def i_LSN(): global PC if L != 0: PC = (PC + 1) & WORDMASK Trace.itrace('LSN') return 1
def i_RSN(): global PC if not TtyIn.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('RSN') return 1
def i_HSF(): global PC if Ptr.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('HSF') return 1
def i_ASZ(): global PC if AC == 0: PC = (PC + 1) & WORDMASK Trace.itrace('ASZ') return 1
def i_RSF(): global PC if TtyIn.ready(): PC = (PC + 1) & WORDMASK Trace.itrace('RSF') return 1
def i_SAL3(indirect, address, instruction): global AC high_bit = AC & HIGHBITMASK value = AC & 007777 AC = (value << 3) | high_bit Trace.itrace('SAL', False, 3) return 1
def i_ISZ(indirect, address, instruction): global PC value = (Memory.get(address, indirect) + 1) & WORDMASK Memory.put(value, address, indirect) if value == 0: PC = (PC + 1) & WORDMASK Trace.itrace('ISZ', indirect, address) return 3 if indirect else 2
def i_JMP(indirect, address, instruction): global PC jmpaddr = EFFADDR(address) if indirect: jmpaddr = Memory.get(jmpaddr, False) PC = jmpaddr & PCMASK Trace.itrace('JMP', indirect, address) return 3 if indirect else 2
def i_JMS(indirect, address, instruction): global PC jmsaddr = EFFADDR(address) if indirect: jmsaddr = Memory.get(jmsaddr, False) Memory.put(PC, jmsaddr, False) PC = (jmsaddr + 1) & PCMASK Trace.itrace('JMS', indirect, address) return 3 if indirect else 2
def i_SAM(indirect, address, instruction): global PC samaddr = EFFADDR(address) if indirect: samaddr = Memory.get(samaddr, False) if AC == Memory.get(samaddr, False): PC = (PC + 1) & PCMASK Trace.itrace('SAM', indirect, address) return 3 if indirect else 2
def i_RAR1(indirect, address, instruction): global AC, L newl = AC & 1 newac = (AC >> 1) | (L << 15) L = newl AC = newac & WORDMASK Trace.itrace('RAR', False, 1) return 1
def i_RAL1(indirect, address, instruction): global AC, L newl = AC >> 15 newac = (AC << 1) | L L = newl AC = newac & WORDMASK Trace.itrace('RAL', False, 1) return 1
def i_SUB(indirect, address, instruction): global AC, L effaddr = EFFADDR(address) AC -= Memory.get(address, indirect) if AC & OVERFLOWMASK: L = not L AC &= WORDMASK Trace.itrace('SUB', indirect, address) return 3 if indirect else 2
def i_LAW_LWC(indirect, address, instruction): global AC if indirect: AC = ((~address) + 1) & WORDMASK Trace.itrace('LWC', False, address) else: AC = address Trace.itrace('LAW', False, address) return 1
def i_XAM(indirect, address, instruction): global AC if indirect: address = Memory.get(address, False) tmp = Memory.get(address, False) Memory.put(AC, address, False) AC = tmp Trace.itrace('XAM', indirect, address) return 3 if indirect else 2