def test_get_stream_blocks(stc, monkeypatch): ctor = CScriptableCreator() project = CStcSystem.Instance().GetObject("project") port = ctor.Create("port", project) def soft_and_hard(port): return "SOFT_AND_HARD" monkeypatch.setattr(tsc, "get_fpga_capability", soft_and_hard) # single (hard) streamblock streamblocks = [ctor.Create("streamblock", port)] # compare handles, proxies are not necessarily comparable all_streamblocks = tsc.get_stream_blocks(port, False) soft_streamblocks = tsc.get_stream_blocks(port, True) assert ([sb.GetObjectHandle() for sb in all_streamblocks] == [streamblocks[0].GetObjectHandle()]) assert soft_streamblocks == [] # one hard, one soft streamblocks += [ctor.Create("streamblock", port)] streamblocks[1].Set("EnableHighSpeedResultAnalysis", False) all_streamblocks = tsc.get_stream_blocks(port, False) soft_streamblocks = tsc.get_stream_blocks(port, True) assert ([sb.GetObjectHandle() for sb in all_streamblocks] == [sb.GetObjectHandle() for sb in streamblocks]) assert ([sb.GetObjectHandle() for sb in soft_streamblocks] == [streamblocks[1].GetObjectHandle()]) # one hard, one soft, one hard inactive, one soft inactive streamblocks += [ctor.Create("streamblock", port)] streamblocks += [ctor.Create("streamblock", port)] streamblocks[2].Set("Active", False) streamblocks[3].Set("Active", False) streamblocks[3].Set("EnableHighSpeedResultAnalysis", False) all_streamblocks = tsc.get_stream_blocks(port, False) soft_streamblocks = tsc.get_stream_blocks(port, True) assert ([sb.GetObjectHandle() for sb in all_streamblocks] == [streamblocks[0].GetObjectHandle(), streamblocks[1].GetObjectHandle()]) assert ([sb.GetObjectHandle() for sb in soft_streamblocks] == [streamblocks[1].GetObjectHandle()])