def test_bus3(dump_vcd, test_verilog):
model = Bus(3, 16)
model.vcd_file = dump_vcd
if test_verilog:
model = TranslationTool(model)
run_test_bus(model, [
[0xdead, 0xbeef, 0xcafe, 0, 0xdead, 0xdead, 0xdead],
[0xdead, 0xbeef, 0xcafe, 1, 0xbeef, 0xbeef, 0xbeef],
[0xdead, 0xbeef, 0xcafe, 2, 0xcafe, 0xcafe, 0xcafe],
])
