def test_ambiFET(self):
idvd_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt')
idvg_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt')
gate_oxide = SiO2(thickness=Value(30, ureg.nanometer))
channel = MoS2(layer_number=1)
substrate = Silicon()
fet = ambiTFT(gate_oxide=gate_oxide,
channel=channel,
width=Value(1, ureg.micrometer),
substrate=substrate,
length=Value(1, ureg.micrometer))
result = FETExtractor(FET=fet,
idvg_path=idvg_path,
idvd_path=idvd_path)
print("~~~~~~TFT Extracted Values~~~~~~")
print("~~~~~~n-type~~~~~~")
print(result.FET.NBranch.Vt_avg)
print(result.FET.NBranch.Vt_fwd)
print(result.FET.NBranch.Vt_bwd)
print(result.FET.NBranch.min_ss)
print("~~~~~~p-type~~~~~~")
print(result.FET.PBranch.Vt_avg)
print(result.FET.PBranch.Vt_fwd)
print(result.FET.PBranch.Vt_bwd)
print(result.FET.PBranch.min_ss)
def test_igzo(self):
# This test models an a-IGZO device with 20nm IGZO, 100nm SiO2 on Si substrate.
# Documentation notes:
# 1. Add material and copy material properties
# 2. Set model in unittest
# 3. Files
# TODO: Change filepaths to point correctly
idvd_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt')
idvg_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt')
gate_oxide = SiO2(thickness=Value(100, ureg.nanometer))
channel = aIGZO(thickness=Value(20, ureg.nanometer))
substrate = Silicon()
fet = pTFT(gate_oxide=gate_oxide,
channel=channel,
width=Value(180, ureg.micrometer),
substrate=substrate,
length=Value(30, ureg.micrometer))
result = FETExtractor(FET=fet,
idvg_path=idvg_path,
idvd_path=idvd_path)
print(result.FET.max_gm)
print(result.FET.max_mobility)
print(result.FET.Vt_avg)
print(result.FET.min_ss)
def test_2DFETExtraction_and_stanford2dsmodel(self):
idvd_path = get_abs_semipy_path(
'SampleData/FETExampleData/MoS2AlOx/MoS2_15AlOxALD_Id_Vd.csv')
idvg_path = get_abs_semipy_path(
'SampleData/FETExampleData/MoS2AlOx/MoS2_15AlOxALD_Id_Vg.txt')
gate_oxide = SiO2(thickness=Value(30.0, ureg.nanometer))
channel = MoS2(layer_number=1)
substrate = Silicon()
fet = nTFT(channel=channel,
gate_oxide=gate_oxide,
length=Value(400, ureg.nanometer),
width=Value(2.2, ureg.micrometer),
substrate=substrate)
result = FETExtractor(FET=fet,
idvg_path=idvg_path,
idvd_path=idvd_path)
fet = result.FET
fet.Rc.set(Value(480.0, ureg.ohm * ureg.micrometer),
input_values={'n': Value(1e13, ureg.centimeter**-2)})
fet.mobility_temperature_exponent.set(Value(0.85, ureg.dimensionless))
fet.max_mobility.set(Value(
35, ureg.centimeter**2 / (ureg.volt * ureg.second)),
input_values={
'Vd': Value(1, ureg.volt),
'Vg': Value(1, ureg.volt)
})
S2DModel = Stanford2DSModel(FET=fet)
Vds = ModelInput(0.0, 5.0, num=40, unit=ureg.volt)
Vgs = ModelInput(0.0, 30.0, num=4, unit=ureg.volt)
ambient_temperature = Value(300, ureg.kelvin)
id = S2DModel.model_output(Vds,
Vgs,
heating=True,
vsat=True,
diffusion=False,
drift=True,
ambient_temperature=ambient_temperature)
plot = IdVdPlot('IdVd')
plot.add_idvd_dataset(result.idvd, marker='o')
for key in id.keys():
if 'Id' in key:
plot.add_data(Vds.range, id[key], linewidth=4.0)
plot.show_plot()
def test_tlmextraction(self):
# Change these filepaths to match TLM data
idvd_path = get_abs_semipy_path(
'SampleData/TLMExampleData/WSe2_Sample_4_Id_Vd.txt') # unused
idvg_path = get_abs_semipy_path('SampleData/TLMExampleData')
widths = Value(4.0, ureg.micrometer)
lengths = Value.array_like(np.array([0.5, 1.0, 2.0, 2.5, 3.0, 3.5]),
unit=ureg.micrometer)
#lengths = Value.array_like(np.array([1.0, 2.0, 0.5]), unit=ureg.micrometer)
#lengths = Value.array_like(np.array([2.0, 0.5, 1.0]), unit=ureg.micrometer)
gate_oxide = SiO2(thickness=Value(30, ureg.nanometer))
channel = MoS2(layer_number=1)
result = TLMExtractor(widths=widths,
lengths=lengths,
gate_oxide=gate_oxide,
channel=channel,
FET_class=nTFT,
idvg_path=idvg_path,
vd_values=[1.0, 2.0],
substrate=Silicon())
result.save_tlm_plots()
def test_idvgdataset(self):
path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt')
dataset = IdVgDataSet(data_path=path)
result = dataset.get_column(column_name='vg_fwd',
master_independent_value_range=[0, 10.0])
self.assertEqual(
result[0][0], Value(0.0, ureg.volt),
'Error in the IdVgDataSet object get column function when requesting master'
' independent value range. Lowest Vg value should be 0.0 volt but is {0}'
.format(result[0][0]))
self.assertEqual(
result[0][-1], Value(9.5, ureg.volt),
'Error in the IdVgDataSet object get column function when requesting master'
' independent value range. Highest Vg value should be 9.5 volt but is {0}'
.format(result[0][-1]))
result, vd = dataset.get_column(column_name='id',
return_set_values=True)
self.assertEqual(
result[0][-1], Value(1.921e-6, ureg.amp),
'Error in the IdVgDataSet object get column function. Highest Id value should '
'be 1.921e-6 amps but is {0}'.format(result[0][-1]))
self.assertEqual(
vd[-1], Value(2.0, ureg.volt),
'Error in the IdVgDataSet object get column function. Highest Vd value should '
'be 2.0 volts but is {0}'.format(result[0][-1]))
result = dataset.get_column_set(column_name='id',
secondary_value=Value(1.0, ureg.volt))
self.assertEqual(
len(result.shape), 1,
'Error in the IdVgDataSet object get column set function. Result should only have '
'1 dimension but it has {0}'.format(len(result.shape)))
"""
Testing for transistor models
"""
import unittest
from SemiPy.Extractors.TLM.TLMExtractor import TLMExtractor
from SemiPy.Devices.Devices.FET.ThinFilmFET import nTFT
from SemiPy.Devices.Materials.Oxides.MetalOxides import SiO2
from SemiPy.Devices.Materials.Semiconductors.BulkSemiconductors import Silicon
from SemiPy.Devices.Materials.TwoDMaterials.TMD import MoS2
from SemiPy.helper.paths import get_abs_semipy_path
from physics.value import Value, ureg
import numpy as np
idvd_path = get_abs_semipy_path(
'SampleData/TLMExampleData/WSe2_Sample_4_Id_Vd.txt') # unused
idvg_path = get_abs_semipy_path('SampleData/TLMExampleData')
widths = Value(4.0, ureg.micrometer)
lengths = Value.array_like(np.array([0.5, 1.0, 2.0, 2.5, 3.0, 3.5]),
unit=ureg.micrometer)
gate_oxide = SiO2(thickness=Value(30, ureg.nanometer))
channel = MoS2(layer_number=1)
result = TLMExtractor(widths=widths,
lengths=lengths,
gate_oxide=gate_oxide,
channel=channel,
FET_class=nTFT,
idvg_path=idvg_path,
vd_values=[1.0, 2.0],
substrate=Silicon())
def test_fetextraction(self):
idvd_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt')
idvg_path = get_abs_semipy_path(
'SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt')
# path = '/home/connor/Documents/Stanford_Projects/Extractions/src/SampleData/FETExampleData/nano_patterning.csv'
# idvd_path = '/home/connor/Documents/Stanford_Projects/Extractions/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt'
# idvg_path = '/home/connor/Documents/Stanford_Projects/Extractions/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt'
#
#idvd_path = '/home/connor/Documents/Stanford_Projects/Extractions/fetextraction/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt'
#idvg_path = '/home/connor/Documents/Stanford_Projects/Extractions/fetextraction/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt'
#idvd_path = '/home/connor/Documents/Stanford_Projects/Extractions/fetextraction/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vd.txt'
#idvg_path = '/home/connor/Documents/Stanford_Projects/Extractions/fetextraction/SemiPy/SampleData/FETExampleData/WSe2_Sample_4_Id_Vg.txt
gate_oxide = SiO2(thickness=Value(30, ureg.nanometer))
channel = MoS2(layer_number=1)
substrate = Silicon()
fet = nTFT(gate_oxide=gate_oxide,
channel=channel,
width=Value(1, ureg.micrometer),
substrate=substrate,
length=Value(1, ureg.micrometer))
# SchottkyModel(fet, )
result = FETExtractor(FET=fet,
idvg_path=idvg_path,
idvd_path=idvd_path)
print(result.FET.Vt_avg)
print(result.FET.Vt_fwd)
print(result.FET.Vt_bwd)
print(result.FET.min_ss)
# nFET data
self.assert_value_equals(result.FET.Vt_avg, Value(3.78, ureg.volt),
'Vt avg')
self.assert_value_equals(result.FET.Vt_bwd, Value(4.06, ureg.volt),
'Vt bwd')
self.assert_value_equals(result.FET.Vt_fwd, Value(3.5, ureg.volt),
'Vt fwd')
self.assert_value_equals(
result.FET.min_ss,
Value(534.15, ureg.micrometer * ureg.millivolt / ureg.ampere),
'min SS')
self.assert_value_equals(
result.FET.max_gm,
Value(3.64, ureg.microsiemens / ureg.micrometer), 'Max Gm')
self.assert_value_equals(
result.FET.max_mobility,
Value(15.82, ureg.centimeter**2 / ureg.second / ureg.volt),
'Max Mobility')
fet = pTFT(gate_oxide=gate_oxide,
channel=channel,
width=Value(1, ureg.micrometer),
length=Value(1, ureg.micrometer),
substrate=substrate)
result = FETExtractor(FET=fet,
idvg_path=idvg_path,
idvd_path=idvd_path)
print(result.FET.min_ss)
from SemiPy.Physics.Modeling.TwoDFETs.Stanford2D import Stanford2DSModel
from SemiPy.Devices.Materials.TwoDMaterials.TMD import MoS2
from SemiPy.Devices.Materials.Oxides.MetalOxides import SiO2
from SemiPy.Devices.Materials.Semiconductors.BulkSemiconductors import Silicon
from SemiPy.Devices.Devices.FET.ThinFilmFET import nTFT
from physics.value import Value, ureg
from SemiPy.Physics.Modeling.BaseModel import ModelInput
from SemiPy.Extractors.Transistor.FETExtractor import FETExtractor
from SemiPy.helper.paths import get_abs_semipy_path
from SemiPy.Plotting.IVPlotting.IVPlot import IdVdPlot
# Import the IdVd and IdVg Data
idvd_path = get_abs_semipy_path(
'SampleData/FETExampleData/MoS2AlOx/MoS2_15AlOxALD_Id_Vd.csv')
idvg_path = get_abs_semipy_path(
'SampleData/FETExampleData/MoS2AlOx/MoS2_15AlOxALD_Id_Vg.txt')
# Create the FET structure
gate_oxide = SiO2(thickness=Value(30.0, ureg.nanometer))
channel = MoS2(layer_number=1)
substrate = Silicon()
fet = nTFT(channel=channel,
gate_oxide=gate_oxide,
length=Value(400, ureg.nanometer),
width=Value(2.2, ureg.micrometer),
substrate=substrate)
# Extract prameters from the FET
result = FETExtractor(FET=fet, idvg_path=idvg_path, idvd_path=idvd_path)