def test_sseq2tseq3_0_bank_addr_generator():
width = 11
T = Array[width, BitIn]
sseq_dim = 2
tseq_dim = 3
lcm_dim = lcm(sseq_dim, tseq_dim)
st_flat_idxs = st_lens_to_vals(sseq_dim, tseq_dim)
# transpose the st_flat_idxs so inner array is on same clock
flat_idxs_inner_per_clock = [[st_flat_idxs[s][t] for s in range(sseq_dim)] for t in range(tseq_dim)]
# banks and addr should write to each clock
banks_per_clock = [[((flat_idx % sseq_dim) + (flat_idx // lcm_dim)) % sseq_dim for flat_idx in flat_idxs_one_clock] for flat_idxs_one_clock in flat_idxs_inner_per_clock]
addr_per_clock = [[flat_idx // sseq_dim for flat_idx in flat_idxs_one_clock] for flat_idxs_one_clock in flat_idxs_inner_per_clock]
testcircuit = DefineSTBankAddrGenerator(sseq_dim, tseq_dim, 0, 1)
tester = fault.Tester(testcircuit, testcircuit.CLK)
for t in range(tseq_dim):
tester.eval()
for s in range(sseq_dim):
tester.circuit.bank.expect(banks_per_clock[t][s])
tester.circuit.addr.expect(addr_per_clock[t][s])
tester.step(2)
compile_and_run(tester)
def test_up_t_invalids_v_delated_true_ce():
iterations = 2
delay = 5
num_out = 4
invalids = 2
test_val = 3
elem_t = ST_Int()
up = DefineUp_T(num_out, invalids, elem_t, has_ce=True, has_valid=True)
tester = fault.Tester(up, up.CLK)
tester.circuit.valid_up = 0
tester.circuit.CE = 1
tester.circuit.I = test_val + 4
for i in range(delay):
tester.step(2)
tester.circuit.valid_up = 1
for i in range(iterations):
for j in range(num_out + invalids):
if j == 0:
tester.circuit.I = test_val + i
else:
tester.circuit.I = test_val + 4
tester.eval()
if j < num_out:
tester.circuit.O.expect(test_val + i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_fifo_basic_1_clock():
num_in = 4
num_iterations = 2
test_vals = [2,4,6,8,1,3,5,9]
delay_amount = 1
in_type = ST_TSeq(num_in, 0, ST_Int())
rshift = DefineFIFO(in_type, delay_amount, has_valid=True)
tester = fault.Tester(rshift, rshift.CLK)
tester.circuit.valid_up = 1
input_counter = 0
output_counter = 0
for i in range(num_iterations):
for j in range(num_in):
tester.print("clk: {}\n".format(i*num_iterations + j))
tester.circuit.I = test_vals[input_counter]
tester.eval()
if i == 0 and j < delay_amount:
tester.circuit.valid_down.expect(0)
else:
tester.circuit.valid_down.expect(1)
tester.circuit.O.expect(test_vals[output_counter])
output_counter = min(output_counter + 1, len(test_vals))
input_counter = min(input_counter + 1, len(test_vals))
tester.step(2)
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def test_serialize_multiple_clocks():
no = 2
io = 0
ni = 2
ii = 1
inputs = [[1, 2], [3, 4]]
wrong_inputs = [5, 6]
outputs = [1, 3, 2, 4]
num_iterations = 2
t = ST_TSeq(ni, ii, ST_Int())
ser = DefineSerialize(no, io, t)
tester = fault.Tester(ser, ser.CLK)
tester.circuit.valid_up = 1
output_counter = 0
for clk in range(num_iterations * (no + io) * t.time()):
if clk % ((no + io) * (ni + ii)) < ni:
tester.circuit.I = inputs[clk % (no + io)]
else:
tester.circuit.I = wrong_inputs
tester.print("clk: {}\n".format(clk))
tester.step(2)
tester.circuit.valid_down.expect(1)
if clk in [0, 1, 3, 4, 6, 7, 9, 10]:
tester.circuit.O.expect(outputs[output_counter])
output_counter += 1
output_counter = output_counter % 4
compile_and_run(tester)
def test_ram_st_TSeq_3_1():
n = 3
i = 1
t = ST_TSeq(n, i, ST_Int())
num = 2
testcircuit = DefineRAM_ST(t, num)
tester = fault.Tester(testcircuit, testcircuit.CLK)
valid_clocks = [(o < n) for o in range(n + i)]
tester.circuit.WE = True
tester.circuit.RE = True
clk = 0
for k in range(2):
for j in range(n + i):
tester.print("clk: {}\n".format(clk))
tester.circuit.WADDR = k
tester.circuit.RADDR = k - 1
tester.circuit.WDATA = j + k * (n + i)
tester.eval()
if k == 1 and valid_clocks[j]:
tester.circuit.RDATA.expect(j)
tester.step(2)
clk += 1
compile_and_run(tester)
def test_bitonic_merge_8_elem():
width = 11
T = Array[width, BitIn]
testcircuit = DefineBitonicMergePow2(T, 8, lambda x: x, 0)
tester = fault.Tester(testcircuit)
inputs = [0, 2, 5, 7, 6, 4, 3, 1]
tester.circuit.I[0] = inputs[0]
tester.circuit.I[1] = inputs[1]
tester.circuit.I[2] = inputs[2]
tester.circuit.I[3] = inputs[3]
tester.circuit.I[4] = inputs[4]
tester.circuit.I[5] = inputs[5]
tester.circuit.I[6] = inputs[6]
tester.circuit.I[7] = inputs[7]
tester.eval()
tester.circuit.O[0].expect(inputs[0])
tester.circuit.O[1].expect(inputs[7])
tester.circuit.O[2].expect(inputs[1])
tester.circuit.O[3].expect(inputs[6])
tester.circuit.O[4].expect(inputs[5])
tester.circuit.O[5].expect(inputs[2])
tester.circuit.O[6].expect(inputs[4])
tester.circuit.O[7].expect(inputs[3])
compile_and_run(tester)
def test_shift_ts():
no = 2
io = 0
ni = 4
test_vals = [[0, 1, 2, 3], [4, 5, 6, 7]]
shifted_test_vals = [[int_to_ignore, int_to_ignore, 0, 1], [2, 3, 4, 5]]
shift_amount = 2
in_type = ST_TSeq(no, io, ST_SSeq(ni, ST_Int()))
rshift = DefineShift_TS(no,
io,
ni,
shift_amount,
in_type.t.t,
has_valid=True)
tester = fault.Tester(rshift, rshift.CLK)
tester.circuit.valid_up = 1
for clk in range(len(test_vals)):
tester.print("clk: {}".format(clk))
set_nested_port(tester, tester.circuit.I, test_vals[clk], 1, 0)
print_nested_port(tester, tester.circuit.I, 1)
tester.print("\n")
tester.eval()
#for i, val in enumerate(test_vals[i*ni+shift_amount:(i+1)*ni+shift_amount]):
print_nested_port(tester, tester.circuit.O, 1)
tester.print("\n")
expect_nested_port(tester, tester.circuit.O, shifted_test_vals[clk], 1,
0)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def check_ram_st(clocks, num_t, tester, valid_clocks, ints_per_clock):
tester.circuit.WE = True
tester.circuit.RE = True
clk = 0
for k in range(num_t):
for j in range(clocks):
tester.print("clk: {}\n".format(clk))
# tester.print("last: %d\n", tester.circuit.last)
#tester.print("inner read counter: %d\n", tester.circuit.ir)
#tester.print("inner write counter: %d\n", tester.circuit.iw)
tester.circuit.WADDR = k
tester.circuit.RADDR = k - 1
if ints_per_clock is not None:
tester.circuit.WDATA = [
ints_per_clock * (j + k * clocks) + i
for i in range(ints_per_clock)
]
else:
tester.circuit.WDATA = j + k * clocks
tester.eval()
if k > 0 and valid_clocks[j]:
if ints_per_clock is not None:
tester.circuit.RDATA.expect([
ints_per_clock * (j + (k - 1) * clocks) + i
for i in range(ints_per_clock)
])
else:
tester.circuit.RDATA.expect(j + (k - 1) * clocks)
tester.step(2)
clk += 1
compile_and_run(tester)
def test_shift_tn_v_always_true_no_ce():
num_in = [3, 2, 2]
test_vals = [i * 2 for i in range(num_in[0] * num_in[1] * num_in[2])]
shift_amount = 1
in_type = ST_TSeq(num_in[0], 0,
ST_TSeq(num_in[1], 0, ST_TSeq(num_in[2], 0, ST_Int())))
num_clocks_per_iteration = len(test_vals)
num_iterations = 2
testcircuit = DefineShift_TN(in_type.n, (2, 2),
in_type.i, (0, 0),
shift_amount,
ST_Int(),
has_valid=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
for clk in range(num_clocks_per_iteration):
tester.print("CLK: {}\n".format(clk))
tester.circuit.I = test_vals[clk] + i
tester.eval()
if clk >= shift_amount:
tester.circuit.O.expect(test_vals[clk - shift_amount] + i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_shift_t_v_always_true_no_ce():
num_in = 4
test_vals = [2, 5, 3, 8]
shift_amount = 1
in_type = ST_TSeq(num_in, 0, ST_Int())
num_clocks_per_iteration = len(test_vals)
num_iterations = 2
testcircuit = DefineShift_T(in_type.n,
in_type.i,
shift_amount,
in_type.t,
has_valid=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
for clk in range(num_clocks_per_iteration):
tester.circuit.I = test_vals[clk] + i
tester.eval()
if clk >= shift_amount:
tester.circuit.O.expect(test_vals[clk - shift_amount] + i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_shift_t_invalid_v_delayed_true_no_ce():
delay = 3
num_in = 5
test_vals = [2, 5, 3, 8, 10]
shift_amount = 1
in_type = ST_TSeq(num_in, 1, ST_Int())
num_clocks_per_iteration = num_in
num_iterations = 2
testcircuit = DefineShift_T(in_type.n,
in_type.i,
shift_amount,
in_type.t,
has_valid=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.valid_up = 0
for i in range(delay):
tester.step(2)
tester.circuit.valid_down.expect(0)
tester.circuit.valid_up = 1
for i in range(num_iterations):
for clk in range(num_clocks_per_iteration):
val_idx = min(clk, len(test_vals) - 1)
tester.circuit.I = test_vals[val_idx] + i
tester.eval()
if clk >= shift_amount:
tester.circuit.O.expect(test_vals[val_idx - shift_amount] + i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_term_empty():
term = DefineTermAnyType(Array[0, Array[8, Bit]])
tester = fault.Tester(term)
tester.circuit.valid_up = 1
if False:
compile_and_run(tester)
def test_diff_sseq_on_diff_component_of_type():
# i would need to improve test bench for this to actually be tested
# just here to verify no errors on wiring. Need to manually check that for now.
input_type = ST_TSeq(
4, 0, ST_TSeq(1, 1, ST_TSeq(4, 0, ST_SSeq(1, ST_SSeq(1, ST_Int())))))
output_type = ST_TSeq(
4, 4, ST_SSeq(1, ST_TSeq(4, 0, ST_SSeq(1, ST_SSeq(1, ST_Int())))))
graph = build_permutation_graph(input_type, output_type)
testcircuit = DefineReshape_ST(input_type, output_type)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.step(2)
compile_and_run(tester)
def test_reg_11():
width = 11
numOut = 1
T = Array[width, BitOut]
testcircuit = DefineRegisterAnyType(T, numOut, has_ce=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.CE = 1
tester.circuit.I = 2
tester.step(2)
tester.circuit.O.expect(2)
compile_and_run(tester)
def test_mux_int_5():
n = 5
T = ST_Int().magma_repr()
testcircuit = DefineMuxAnyType(T, n)
tester = fault.Tester(testcircuit)
for i in range(n):
tester.circuit.data[i] = i
tester.circuit.sel = 2
tester.eval()
tester.circuit.out.expect(2)
compile_and_run(tester)
def test_map_merge_rv_ce():
width = 11
numIn = 13
numUp = 5
T = Array[width, BitIn]
args = ['I', In(Array[numIn, T]), 'O',
Out(Array[numIn, T])] + ClockInterface(
True, True) + ready_valid_interface
testcircuit = DefineCircuit('Test_Map_Merge', *args)
ups = DefineNativeMapParallel(numIn,
DefineUpsampleSequential(
numUp, 1, T, True, True),
merge_ready_valid_ce_reset=True)()
wire(ups.I, testcircuit.I)
wire(ups.O, testcircuit.O)
wire(ups.CE, testcircuit.CE)
wire(ups.RESET, testcircuit.RESET)
wire(ups.valid_down, testcircuit.valid_down)
wire(ups.valid_up, testcircuit.valid_up)
wire(ups.ready_down, testcircuit.ready_down)
wire(ups.ready_up, testcircuit.ready_up)
EndCircuit()
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.ready_down = True
tester.circuit.valid_up = True
tester.circuit.CE = True
tester.circuit.RESET = False
for i in range(numIn):
tester.circuit.I[i] = i
for i in range(numUp):
tester.eval()
for j in range(numIn):
tester.circuit.O[j].expect(j)
#tester.print(f"circuit ready_up: %d\n", testcircuit.ready_up)
#tester.print(f"first upsample ready_up: %d\n", testcircuit._instances[0]._instances[0].defn.ready_up)
#tester.print(f"first upsample ready_down: %d\n", testcircuit._instances[0]._instances[0].defn.ready_down)
#tester.print(f"first upsample valid_up: %d\n", testcircuit._instances[0]._instances[0].defn.valid_up)
#tester.print(f"first upsample valid_down: %d\n", testcircuit._instances[0]._instances[0].defn.valid_down)
tester.circuit.ready_up.expect(i == 0)
tester.circuit.valid_down.expect(True)
tester.step(2)
for i in range(numIn):
tester.circuit.I[i] = 0
compile_and_run(tester)
def test_ram_1_13():
width = 11
numOut = 1
T = Array[width, BitOut]
testcircuit = DefineRAMAnyType(T, numOut)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.WE = True
tester.circuit.RADDR = 0
tester.circuit.WADDR = 0
tester.circuit.WDATA = 2
tester.step(2)
tester.circuit.RDATA.expect(2)
compile_and_run(tester)
def test_lut_11_13():
width = 11
numOut = 13
T = Array[width, BitOut]
init = [builtins.tuple(int2seq(i, width)) for i in range(4, numOut + 4)]
testcircuit = DefineLUTAnyType(T, numOut, builtins.tuple(init))
tester = fault.Tester(testcircuit, testcircuit.CLK)
for i in range(numOut):
tester.circuit.addr = i
tester.eval()
tester.circuit.data.expect(i + 4)
compile_and_run(tester)
def test_down_s():
num_out = 1
test_val = 3
down = DefineDown_S(1, 0, ST_Int(), has_valid=True)
tester = fault.Tester(down, down.CLK)
tester.circuit.valid_up = 1
tester.circuit.I[0] = test_val
tester.eval()
for i in range(num_out):
tester.circuit.O[i].expect(test_val)
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def test_reg_tuple_11_and_12():
width0 = 11
width1 = 12
numOut = 1
T = Tuple(Array[width0, BitOut], Array[width1, BitOut])
testcircuit = DefineRegisterAnyType(T, numOut, has_ce=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.CE = 1
tester.circuit.I[0] = 2
tester.circuit.I[1] = 3
tester.step(2)
tester.circuit.O[0].expect(2)
tester.circuit.O[1].expect(3)
compile_and_run(tester)
def test_reg_array_of_array():
width = 11
num = 2
numOut = 1
T = Array[num, Array[width, BitOut]]
testcircuit = DefineRegisterAnyType(T, numOut, has_ce=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.CE = 1
tester.circuit.I[0] = 2
tester.circuit.I[1] = 3
tester.step(2)
tester.circuit.O[0].expect(2)
tester.circuit.O[1].expect(3)
compile_and_run(tester)
def test_up_s():
num_out = 2
test_val = 3
elem_t = ST_Int()
up = DefineUp_S(num_out, elem_t, True)
tester = fault.Tester(up, up.CLK)
tester.circuit.valid_up = 1
tester.circuit.I[0] = test_val
tester.eval()
for i in range(num_out):
tester.circuit.O[i].expect(test_val)
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def test_term():
width = 11
T = Array[width, BitIn]
args = ['I', In(T), 'O', Out(T)]
testcircuit = DefineCircuit('Test_Term', *args)
wire(testcircuit.I, testcircuit.O)
term = TermAnyType(T)
t_const = DefineCoreirConst(width, 0)()
wire(t_const.O, term.I)
EndCircuit()
tester = fault.Tester(testcircuit)
tester.circuit.I = 2
tester.eval()
tester.circuit.O.expect(2)
compile_and_run(tester)
def test_ram_11_13():
width = 11
numOut = 13
T = Array[width, BitOut]
testcircuit = DefineRAMAnyType(T, numOut)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.WE = True
for i in range(numOut + 1):
tester.circuit.RADDR = i % numOut
tester.circuit.WADDR = i % numOut
tester.circuit.WDATA = i % numOut
tester.step(2)
tester.circuit.RDATA.expect(i % numOut)
compile_and_run(tester)
def test_fault_shift_s():
num_in = 4
test_vals = [2, 5, 3, 8]
shift_amount = 2
in_type = ST_SSeq(num_in, ST_Int())
rshift = DefineShift_S(num_in, shift_amount, in_type.t, has_valid=True)
tester = fault.Tester(rshift, rshift.CLK)
tester.circuit.valid_up = 1
for i, val in enumerate(test_vals):
tester.circuit.I[i] = val
tester.eval()
for i, val in enumerate(test_vals[shift_amount:]):
tester.circuit.O[i + shift_amount].expect(test_vals[i])
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def test_reduce_s_basic():
num_in = 4
num_iterations = 2
test_vals = [2,4,6,8,1,3,5,9]
outputs = [20,18]
red = DefineReduce_S(num_in, DefineAdd_Atom(), has_valid=True)
tester = fault.Tester(red, red.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
tester.print("clk: {}\n".format(i))
for j in range(num_in):
tester.circuit.I[j] = test_vals[i*num_in + j]
tester.step(2)
tester.circuit.valid_down.expect(1)
tester.circuit.O[0].expect(outputs[i])
compile_and_run(tester)
def test_rom_11_13():
width = 11
numOut = 13
T = Array[width, BitOut]
init = [builtins.tuple(int2seq(i)) for i in range(4, numOut+4)]
return
testcircuit = DefineROMAnyType(T, width, builtins.tuple(init))
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.RE = True
for i in range(numOut):
tester.circuit.RADDR = i
tester.step(2)
tester.circuit.RDATA.expect(i + 4)
compile_and_run(tester)
def test_shift_tn_inner_invalid_elem_invalid_v_always_true_no_ce():
num_in = [3, 2, 2]
test_vals = [i * 2 for i in range(num_in[0] * num_in[1] * num_in[2])]
shift_amount = 1
iis = (2, 1)
num_iterations = 2
testcircuit = DefineShift_TN(num_in[0], (2, 2),
0,
iis,
shift_amount,
ST_TSeq(1, 2, ST_Int()),
has_valid=True)
tester = fault.Tester(testcircuit, testcircuit.CLK)
tester.circuit.valid_up = 1
for i in range(num_iterations):
for clk_outer in range(num_in[0]):
for clk_inner in range(num_in[1] + iis[0]):
for clk_ii in range(num_in[2] + iis[1]):
for clk_innermost in range(0, 3):
tester.print("clk_outer: {}\n".format(clk_outer))
tester.print("clk_inner: {}\n".format(clk_inner))
tester.print("clk_ii: {}\n".format(clk_ii))
val_idx = clk_outer * 4 + min(
clk_inner, num_in[1] - 1) * 2 + min(
clk_ii, num_in[2] - 1)
in_val = test_vals[val_idx] + i + (
0 if clk_inner < 2 and clk_ii < 2
and clk_innermost == 0 else 110)
tester.circuit.I = in_val
tester.print("I: {}\n".format(str(in_val)))
tester.eval()
tester.print("O: %d\n", tester.circuit.O)
#tester.print("inner_valid: %d\n", tester.circuit.inner_valid)
if val_idx >= shift_amount and clk_inner < 2 and clk_ii < 2 and clk_innermost == 0:
tester.circuit.O.expect(test_vals[val_idx -
shift_amount] +
i)
tester.circuit.valid_down.expect(1)
tester.step(2)
compile_and_run(tester)
def test_up_s_sseq():
n = 2
num_out = 2
test_vals = [3, 5]
elem_t = ST_SSeq(n, ST_Int())
up = DefineUp_S(num_out, elem_t, True)
tester = fault.Tester(up, up.CLK)
tester.circuit.valid_up = 1
for i, v in enumerate(test_vals):
tester.circuit.I[0][i] = v
tester.eval()
for i in range(num_out):
for j, v in enumerate(test_vals):
tester.circuit.O[i][j].expect(v)
tester.circuit.valid_down.expect(1)
compile_and_run(tester)
def test_serialize_basic():
n = 5
i = 0
inputs = list(range(n))
num_iterations = 2
t = ST_Int()
ser = DefineSerialize(n, i, t)
tester = fault.Tester(ser, ser.CLK)
tester.circuit.valid_up = 1
tester.circuit.I = inputs
for clk in range(num_iterations * (n + i)):
tester.print("clk: {}\n".format(clk))
tester.step(2)
tester.circuit.valid_down.expect(1)
tester.circuit.O.expect(inputs[clk % n])
compile_and_run(tester)
