str(value(counter)) + "\n")
end_architecture()
@do_simulation
def data_record_tb_sim(OutputPath, f=None):
tb1 = data_record_tb()
return tb1
def test_data_record_tb_sim():
return data_record_tb_sim("tests/data_record_tb_sim/")
add_test("data_record_tb_sim", test_data_record_tb_sim)
@vhdl_conversion
def data_record_tb_2vhdl(OutputPath, f=None):
tb1 = data_record_tb()
return tb1
def test_data_record_tb_2vhdl():
return data_record_tb_2vhdl("tests/data_record_tb/")
add_test("data_record_tb_2vhdl", test_data_record_tb_2vhdl)
", " + str(value(dut.ConfigOut.data)) + '\n')
end_architecture()
@do_simulation
def InputDelay_sim(OutputPath, f):
tb = InputDelay_tb_sim(f)
return tb
def test_InputDelay_sim():
return InputDelay_sim("tests/ex1/")
add_test("InputDelay_sim", test_InputDelay_sim)
@vhdl_conversion
def InputDelay2vhdl(OutputPath):
tb = InputDelay_tb()
return tb
def test_InputDelay2vhdl():
return InputDelay2vhdl("tests/ex1_vhdl/")
add_test("InputDelay2vhdl", test_InputDelay2vhdl)
from argg_hdl.argg_hdl_test_handler import add_test
@vhdl_conversion
def clk_generator_test(OutputFolder):
clkgen = ahe.clk_generator()
return clkgen
def test_clk_generator():
return clk_generator_test("tests/example1/")
add_test("clk_generator", test_clk_generator)
class tb_clk_generator(v_entity):
def __init__(self, f):
super().__init__()
self.f = f
self.architecture()
@architecture
def architecture(self):
clkgen = ahe.clk_generator()
data = v_slv(32, 0)
@rising_edge(clkgen.clk)
end_architecture()
@do_simulation
def fifo_cc_tb_sim(OutputPath, f=None):
tb1 = fifo_cc_tb()
return tb1
def test_fifo_cc_tb_sim():
return fifo_cc_tb_sim("tests/native_fifo_sim")
add_test("fifo_cc_tb_sim", test_fifo_cc_tb_sim)
@vhdl_conversion
def fifo_cc_tb_2vhdl(OutputPath, f=None):
tb1 = fifo_cc_tb()
return tb1
def test_fifo_cc_tb_2vhdl():
return fifo_cc_tb_2vhdl("tests/native_fifo")
add_test("fifo_cc_tb_2vhdl", test_fifo_cc_tb_2vhdl)
counter << 0
myState << myState2
printf(repr(counter) + "; "+ repr(myState)+ "\n")
end_architecture()
@do_simulation
def enum_TB_sim(OutputPath, f= None):
tb1 = enum_TB()
return tb1
def test_enum_TB_sim():
return enum_TB_sim("tests/enumTest_sim")
add_test("enum_TB_sim", test_enum_TB_sim)
@vhdl_conversion
def enum_TB_2vhdl(OutputPath, f= None):
tb1 = enum_TB()
return tb1
def test_enum_TB_2vhdl():
return enum_TB_2vhdl("tests/enumTest")
add_test("enum_TB_2vhdl", test_enum_TB_2vhdl)
ax_in.Send_end_Of_Stream()
end_architecture()
@do_simulation
def cmd_tb_sim(OutputPath, f=None):
tb1 = cmd_tb()
return tb1
def test_cmd_tb_sim():
return cmd_tb_sim("tests/cmd_tb_sim")
add_test("cmd_tb_sim", test_cmd_tb_sim)
@vhdl_conversion
def cmd_tb_2vhdl(OutputPath, f=None):
tb1 = cmd_tb()
return tb1
def test_cmd_tb_2vhdl():
return cmd_tb_2vhdl("tests/cmd_tb/")
add_test("cmd_tb_2vhdl", test_cmd_tb_2vhdl)
str(value(fir1.i_data)) + "; " + str(value(fir1.o_data)) +
"\n")
end_architecture()
@do_simulation
def fir_basic_tb_sim(OutputPath, f=None):
tb = fir_basic_tb()
return tb
def test_fir_basic_tb_sim():
return fir_basic_tb_sim("tests/fir_1_sim", 20000)
add_test("fir_basic_tb_sim", test_fir_basic_tb_sim)
@vhdl_conversion
def fir_basic_tb2vhdl(OutputPath):
gSystem = system_globals()
tb1 = fir_basic(v_sl())
return tb1
def test_fir_basic_tb2vhdl():
return fir_basic_tb2vhdl("tests/fir_1")
add_test("fir_basic_tb2vhdl", test_fir_basic_tb2vhdl)
vs_impl.clk << clkgen.clk
end_architecture()
@do_simulation
def var_sig_tb_sim(OutputPath, f=None):
tb1 = var_sig_tb()
return tb1
def test_var_sig_tb_sim():
return var_sig_tb_sim("tests/var_sig_class_sim/")
add_test("var_sig_tb_sim", test_var_sig_tb_sim)
@vhdl_conversion
def var_sig_tb_2vhdl(OutputPath, f=None):
tb1 = var_sig_tb()
return tb1
def test_RamHandler_2vhdl():
return var_sig_tb_2vhdl("tests/var_sig_class/")
#add_test("var_sig_tb_2vhdl", test_RamHandler_2vhdl)
| axiFifo(clkgen.clk) \
| axiFifo(clkgen.clk, depth = 5) \
| axiPrint(clkgen.clk)
end_architecture()
@do_simulation
def test_bench_axi_fifo_sim(OutputPath, f=None):
tb = test_bench_axi_fifo()
return tb
def test_test_bench_axi_fifo_sim():
return test_bench_axi_fifo_sim("tests/axi_fifo_sim/")
add_test("axi_fifo_sim", test_test_bench_axi_fifo_sim)
@vhdl_conversion
def test_bench_axi_fifo_2vhdl(OutputPath, f=None):
tb = test_bench_axi_fifo()
return tb
def test_test_bench_axi_fifo_2vhdl():
return test_bench_axi_fifo_2vhdl("tests/axi_fifo/")
add_test("axi_fifo_2vhdl", test_test_bench_axi_fifo_2vhdl)
self.TARGET_TB_in \
| \
edge_det
edge_det \
| trigger_scaler(self.gSystem) \
|\
self.reg_out
edge_det\
| package_maker(self.gSystem ) \
| ax_fifo(self.gSystem.clk, trigger_bits_pack())\
| \
self.TX_triggerBits
end_architecture()
@vhdl_conversion
def trigger_bits_test2vhdl(OutputPath, f= None):
tb = tb_edge_detection(globals_t())
return tb
def test_trigger_bits_test2vhdl():
return trigger_bits_test2vhdl("tests/trigger_bits_test2vhdl/")
add_test("trigger_bits_test2vhdl", test_trigger_bits_test2vhdl)
)
end_architecture()
@do_simulation
def slice_TB_sim(OutputPath, f=None):
tb1 = slice_TB()
return tb1
def test_slice_TB_sim():
return slice_TB_sim("tests/slice_TB_sim/")
add_test("slice_TB_sim", test_slice_TB_sim)
@vhdl_conversion
def slice_TB_2vhdl(OutputPath, f=None):
tb1 = slice_TB()
return tb1
def test_slice_TB_2vhdl():
return slice_TB_2vhdl("tests/slice_TB/")
add_test("slice_TB_2vhdl", test_slice_TB_2vhdl)
if addr_out > 8:
addr_out << 0
end_architecture()
@do_simulation
def RamHandler_sim(OutputPath, f= None):
tb1 = ramHandler_tb()
return tb1
def test_RamHandler_sim():
return RamHandler_sim("tests/RamHandler_sim/")
add_test("RamHandler_sim", test_RamHandler_sim)
@vhdl_conversion
def RamHandler_2vhdl(OutputPath, f= None):
tb1 = ramHandler_tb()
return tb1
def test_RamHandler_2vhdl():
return RamHandler_2vhdl("tests/RamHandler/")
add_test("RamHandler_2vhdl", test_RamHandler_2vhdl)