def input_mu(self, data): """ Retrieves the accumulated values for one frame from the ROI engines. Blocks until values are available. The input list must be a list of integers of the same length as there are enabled ROI engines. This method replaces the elements of the input list with the outputs of the enabled ROI engines, sorted by number. If the number of elements in the list does not match the number of ROI engines that produced output, an exception will be raised during this call or the next. """ channel = self.channel_base + 1 sentinel = rtio_input_data(channel) if sentinel != self.sentinel: raise OutOfSyncException for i in range(len(data)): roi_output = rtio_input_data(channel) if roi_output == self.sentinel: raise OutOfSyncException data[i] = roi_output
def read(self, addr): """Read from servo memory. This method does not advance the timeline but consumes all slack. :param addr: Memory location address. """ rtio_output(now_mu(), self.channel, addr, 0) return rtio_input_data(self.channel)
def read(self, addr): """Read parameter This method does not advance the timeline but consumes all slack. :param addr: Memory location address. """ rtio_output((self.channel << 8) | addr, 0) return rtio_input_data(self.channel)
def read8(self, addr) -> TInt32: """Read from FPGA register. :param addr: Address to read from (7 bit) :return: Data read (8 bit) """ rtio_output((self.channel_base << 8) | (addr & 0x7f), 0) response = rtio_input_data(self.channel_base) return response >> self.miso_delay
def enable_source(self, adr, idx): self.core.break_realtime() rtio_output(self.channel << 8 | (adr + 2) << 1 | 0, 0) delay_mu(8) value = rtio_input_data(self.channel) delay_mu(10000) value |= (1 << idx) rtio_output(self.channel << 8 | (adr + 2) << 1 | 1, value) delay_mu(8)
def sample_get(self): """Returns the value of a sample previously obtained with :meth:`sample_input`. Multiple samples may be queued (using multiple calls to :meth:`sample_input`) into the RTIO FIFOs and subsequently read out using multiple calls to this function. This function does not interact with the time cursor.""" return rtio_input_data(self.channel)
def read(self): """Read SPI data submitted by the SPI core. For bit alignment and bit ordering see :meth:`set_config`. This method does not alter the timeline. :return: SPI input data. """ return rtio_input_data(self.channel)
def read(self, addr): """Read from Fastino register. TODO: untested :param addr: Address to read from. :return: The data read. """ rtio_output(self.channel | addr | 0x80) return rtio_input_data(self.channel >> 8)
def read(self, addr): """Read from servo memory. This method does not advance the timeline but consumes all slack. :param addr: Memory location address. """ value = (addr >> 8) << COEFF_WIDTH addr = addr & 0xff rtio_output((self.channel << 8) | addr, value) return rtio_input_data(self.channel)
def watch_stay_on(self): """Checks that the input is at a high level at the position of the time cursor and keep checking until :meth:`watch_done` is called. Returns ``True`` if the input is high. A call to this function must always be followed by an eventual call to :meth:`watch_done` (use e.g. a try/finally construct to ensure this). The time cursor is not modified by this function. """ rtio_output(self.target_sample, 2) # gate falling return rtio_input_data(self.channel) == 1
def read(self, addr): """Read parameter. This method does not advance the timeline but consumes all slack. Args: addr: Memory location address. Returns: Value of the ``Entangler`` setting (register) that you are querying. """ rtio_output((self.channel << 8) | addr, 0) return rtio_input_data(self.channel)
def fetch_count(self) -> TInt32: """Wait for and return count total from previously requested input event. It is valid to trigger multiple gate periods without immediately reading back the count total; the results will be returned in order on subsequent fetch calls. This function blocks until a result becomes available. """ count = rtio_input_data(self.channel) if count == self.counter_max: raise CounterOverflow( "Input edge counter overflow on RTIO channel {0}", int64(self.channel)) return count
def input_async(self): """Retrieves data read asynchronously from the ``data`` register. :meth:`input_async` must match a preeeding :meth:`read_async`. """ return rtio_input_data(self.channel)
def _get_xfer_sync(self): rtio_output(now_mu(), self.channel, SPI_XFER_ADDR | SPI_RT2WB_READ, 0) return rtio_input_data(self.channel)
def watch_stay_off(self): """Like :meth:`watch_stay_on`, but for low levels.""" rtio_output(self.target_sample, 1) # gate rising return rtio_input_data(self.channel) == 0
def _get_config_sync(self): rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ, 0) return rtio_input_data(self.channel)
def read_rt(self) -> TInt32: rtio_output((self.channel << 8) | self.address << 1 | 0, 0) delay_mu(1) return rtio_input_data(self.channel)
def watch_stay_off(self): """Like ``watch_stay_on``, but for low levels.""" rtio_output(now_mu(), self.channel, 3, 1) # gate rising return rtio_input_data(self.channel) == 0