def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0(DRTIOSatellite( self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, **kwargs) if with_sawg: warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.") platform = self.platform rtio_clk_freq = 150e6 self.submodules += Microscope(platform.request("serial", 1), self.clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier( platform, rtio_clk_freq) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0( DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command( "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)
def __init__(self, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, ident=artiq_version, **kwargs) platform = self.platform rtio_channels = [] for i in range(8): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": phy = ttl_simple.InOut(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable_n").eq(1) # 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( clock_pads=platform.request("si5324_clkout"), tx_pads=platform.request("sfp_tx"), rx_pads=platform.request("sfp_rx"), sys_clk_freq=self.clk_freq) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer0 = rx0(gtx_7series.RXSynchronizer( self.transceiver.rtio_clk_freq, initial_phase=180.0)) self.submodules.drtio0 = rx0(DRTIOSatellite( self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0)) self.csr_devices.append("rx_synchronizer0") self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6) si5324_clkin = platform.request("si5324_clkin") self.specials += \ Instance("OBUFDS", i_I=ClockSignal("rtio_rx0"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None platform.add_extension(ad9154_fmc_ebz) ad9154_spi = platform.request("ad9154_spi") self.comb += ad9154_spi.en.eq(1) self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) self.csr_devices.append("converter_spi") self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( platform.lookup_request("clk200"), self.transceiver.txoutclk, self.transceiver.rxoutclk)
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, **kwargs) RTMCommon.__init__(self) add_identifier(self, suffix=".without-sawg" if not with_sawg else "") self.config["HMC830_REF"] = "150" platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) self.csr_devices.append("ad9154_crg") self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend( rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs for phy in sawg.phys) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0( DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command( "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( self.drtio0.coarse_ts, self.ad9154_crg.jref) self.csr_devices.append("sysref_sampler") rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)
def __init__(self, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, **kwargs) platform = self.platform rtio_clk_freq = 150e6 rtio_channels = [] phy = ttl_simple.Output(platform.request("user_led", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") si5324_clkout = platform.request("si5324_clkout") si5324_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, o_O=si5324_clkout_buf) qpll_drtio_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings) self.submodules += qpll self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0) self.submodules.transceiver = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.drtio0 = rx0( DRTIOSatellite(self.transceiver.channels[0], rtio_channels)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) si5324_clkin = platform.request("si5324_clkin") self.specials += \ Instance("OBUFDS", i_I=ClockSignal("rtio_rx0"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None rtio_clk_period = 1e9 / rtio_clk_freq gtp = self.transceiver.gtps[0] platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk)
def __init__(self, cfg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, ident=artiq_version, **kwargs) platform = self.platform rtio_channels = [] for i in range(8): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.comb += platform.request("sfp_tx_disable_n").eq(1) if cfg == "simple_gbe": # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # simple TTLs transceiver = gtx_7series.GTX_1000BASE_BX10 elif cfg == "sawg_3g": # 3Gb link, 150MHz RTIO clock # with SAWG on local RTIO and AD9154-FMC-EBZ platform.add_extension(ad9154_fmc_ebz) ad9154_spi = platform.request("ad9154_spi") self.comb += ad9154_spi.en.eq(1) self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) self.csr_devices.append("converter_spi") self.config["CONVERTER_SPI_DAC_CS"] = 0 self.config["CONVERTER_SPI_CLK_CS"] = 1 self.config["HAS_AD9516"] = None transceiver = gtx_7series.GTX_3G else: raise ValueError self.submodules.transceiver = transceiver( clock_pads=platform.request("si5324_clkout"), tx_pads=platform.request("sfp_tx"), rx_pads=platform.request("sfp_rx"), sys_clk_freq=self.clk_freq) self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer( self.transceiver.rtio_clk_freq, initial_phase=180.0) self.submodules.drtio = DRTIOSatellite( self.transceiver, rtio_channels, self.rx_synchronizer) self.csr_devices.append("rx_synchronizer") self.csr_devices.append("drtio") self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]), self.drtio.aux_controller.bus) self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6) si5324_clkin = platform.request("si5324_clkin") self.specials += \ Instance("OBUFDS", i_I=ClockSignal("rtio_rx"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( platform.lookup_request("clk200"), self.transceiver.txoutclk, self.transceiver.rxoutclk)