def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
self.platform.add_extension(_sma_spi)
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
phy = spi2.SPIMaster(self.platform.request("sma_spi"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self):
platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io)
rtio_channels = []
clock_generators = []
# All TTL channels are In+Out capable
for i in range(40):
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
for i in range(2):
phy = ttl_simple.ClockGen(platform.request("clkout", i))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
# user SMA on KC705 board
phy = ttl_serdes_7series.InOut_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# AMS101 DAC on KC705 XADC header - optional
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# add clock generators after TTLs
rtio_channels += clock_generators
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(4):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
for backplane_offset in range(2):
phy = dds.AD9914(platform.request("dds", backplane_offset),
12,
onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def add_std(cls, target, eem, spi, ttl, iostandard=default_iostandard):
cls.add_extension(target, eem, spi, ttl, iostandard=iostandard)
for i in range(len(spi)):
phy = spi2.SPIMaster(
target.platform.request("dio{}_spi{}_p".format(eem, i)),
target.platform.request("dio{}_spi{}_n".format(eem, i))
)
target.submodules += phy
target.rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=4))
dci = iostandard(eem).name == "LVDS"
for i, (_, ttl_cls, edge_counter_cls) in enumerate(ttl):
pads = target.platform.request("dio{}".format(eem), i)
phy = ttl_cls(pads.p, pads.n, dci=dci)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
if edge_counter_cls is not None:
state = getattr(phy, "input_state", None)
if state is not None:
counter = edge_counter_cls(state)
target.submodules += counter
target.rtio_channels.append(rtio.Channel.from_phy(counter))
def add_std(cls, target, eem, eem_aux, ttl_out_cls, dds_type, sync_gen_cls=None, iostandard=default_iostandard):
cls.add_extension(target, eem, eem_aux, iostandard=iostandard)
spi_phy = spi2.SPIMaster(target.platform.request("urukul{}_spi_p".format(eem)),
target.platform.request("urukul{}_spi_n".format(eem)))
target.submodules += spi_phy
target.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem))
if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM
phy = sync_gen_cls(pad=pads.p, pad_n=pads.n, ftw_width=4)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
pads = target.platform.request("urukul{}_io_update".format(eem))
io_upd_phy = ttl_out_cls(pads.p, pads.n)
target.submodules += io_upd_phy
target.rtio_channels.append(rtio.Channel.from_phy(io_upd_phy))
dds_monitor = dds.UrukulMonitor(spi_phy, io_upd_phy, dds_type)
target.submodules += dds_monitor
spi_phy.probes.extend(dds_monitor.probes)
if eem_aux is not None:
for signal in "sw0 sw1 sw2 sw3".split():
pads = target.platform.request("urukul{}_{}".format(eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def add_std(cls,
target,
eem,
eem_aux,
ttl_out_cls,
sync_gen_cls=None,
iostandard="LVDS_25"):
cls.add_extension(target, eem, eem_aux, iostandard=iostandard)
phy = spi2.SPIMaster(
target.platform.request("urukul{}_spi_p".format(eem)),
target.platform.request("urukul{}_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request(
"urukul{}_dds_reset_sync_in".format(eem))
pad = Signal(reset=0)
target.specials += DifferentialOutput(pad, pads.p, pads.n)
if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM
phy = sync_gen_cls(pad, ftw_width=4)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
pads = target.platform.request("urukul{}_io_update".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
if eem_aux is not None:
for signal in "sw0 sw1 sw2 sw3".split():
pads = target.platform.request("urukul{}_{}".format(
eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def add_std(cls, target, eem, eem_aux, ttl_out_cls, iostandard="LVDS_25"):
cls.add_extension(target, eem, eem_aux, iostandard=iostandard)
phy = spi2.SPIMaster(
target.platform.request("sampler{}_adc_spi_p".format(eem)),
target.platform.request("sampler{}_adc_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
phy = spi2.SPIMaster(
target.platform.request("sampler{}_pgia_spi_p".format(eem)),
target.platform.request("sampler{}_pgia_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request("sampler{}_cnv".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
sdr = target.platform.request("sampler{}_sdr".format(eem))
target.specials += DifferentialOutput(1, sdr.p, sdr.n)
def add_std(cls, target, eem, ttl_out_cls, iostandard="LVDS_25"):
cls.add_extension(target, eem, iostandard=iostandard)
phy = spi2.SPIMaster(target.platform.request("novogorny{}_spi_p".format(eem)),
target.platform.request("novogorny{}_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
pads = target.platform.request("novogorny{}_cnv".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_urukul("eem1", "eem0"))
platform.add_extension(_dio("eem2"))
platform.add_extension(_dio("eem3"))
platform.add_extension(_dio("eem4"))
platform.add_extension(_dio("eem5"))
platform.add_extension(_dio("eem6"))
# EEM clock fan-out from Si5324, not MMCX
self.comb += platform.request("clk_sel").eq(1)
# EEM2-6: TTL
rtio_channels = []
for i in range(40):
eem_offset, port = divmod(i, 8)
pads = platform.request("eem{}".format(2 + eem_offset), port)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM0, EEM1: Urukul
phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
self.platform.request("eem1_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem1_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem1_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def add_std(cls, target, eem, ttl_out_cls):
cls.add_extension(target, eem)
phy = spi2.SPIMaster(
target.platform.request("zotino{}_spi_p".format(eem)),
target.platform.request("zotino{}_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "ldac_n clr_n".split():
pads = target.platform.request("zotino{}_{}".format(eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def add_std(cls, target, eem, ttl_out_cls, iostandard=default_iostandard):
cls.add_extension(target, eem, iostandard=iostandard)
phy = spi2.SPIMaster(
target.platform.request("mirny{}_spi_p".format(eem)),
target.platform.request("mirny{}_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(4):
pads = target.platform.request("mirny{}_io{}".format(eem, i))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def add_std(cls, target, eem, ttl_out_cls, iostandard="LVDS_25"):
cls.add_extension(target, eem, iostandard=iostandard)
spi_phy = spi2.SPIMaster(target.platform.request("zotino{}_spi_p".format(eem)),
target.platform.request("zotino{}_spi_n".format(eem)))
target.submodules += spi_phy
target.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
pads = target.platform.request("zotino{}_ldac_n".format(eem))
ldac_phy = ttl_out_cls(pads.p, pads.n)
target.submodules += ldac_phy
target.rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
pads = target.platform.request("zotino{}_clr_n".format(eem))
clr_phy = ttl_out_cls(pads.p, pads.n)
target.submodules += clr_phy
target.rtio_channels.append(rtio.Channel.from_phy(clr_phy))
dac_monitor = ad53xx_monitor.AD53XXMonitor(spi_phy.rtlink, ldac_phy.rtlink)
target.submodules += dac_monitor
spi_phy.probes.extend(dac_monitor.probes)
def add_std(cls, target, eem, eem_aux, ttl_out_cls):
cls.add_extension(target, eem, eem_aux)
phy = spi2.SPIMaster(
target.platform.request("urukul{}_spi_p".format(eem)),
target.platform.request("urukul{}_spi_n".format(eem)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request("urukul{}_dds_reset".format(eem))
target.specials += DifferentialOutput(0, pads.p, pads.n)
pads = target.platform.request("urukul{}_io_update".format(eem))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
if eem_aux is not None:
for signal in "sw0 sw1 sw2 sw3".split():
pads = target.platform.request("urukul{}_{}".format(
eem, signal))
phy = ttl_out_cls(pads.p, pads.n)
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy))
def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.1"
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
# TODO: grabber on eem0->eemB eem1->eemA
platform.add_extension(_urukul("eem3", "eem2"))
platform.add_extension(_dio("eem4"))
platform.add_extension(_zotino("eem5"))
platform.add_extension(_zotino("eem6"))
# EEM4: TTL
rtio_channels = []
for i in range(8):
pads = platform.request("eem4", i)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM2, EEM3: Urukul
phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"),
self.platform.request("eem3_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem3_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem3_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM5, EEM6: Zotino
for i in (5, 6):
phy = spi2.SPIMaster(
self.platform.request("eem{}_spi_p".format(i)),
self.platform.request("eem{}_spi_n".format(i)))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "ldac_n clr_n".split():
pads = platform.request("eem{}_{}".format(i, signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
for i in range(3):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128))
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.InOut_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(3):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
phy = ttl_simple.Output(s)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
self.platform.request("zotino_spi_n"))
self.submodules += sdac_phy
rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
pads = platform.request("zotino_ldac")
ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += ldac_phy
rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink,
ldac_phy.rtlink)
self.submodules += dac_monitor
sdac_phy.probes.extend(dac_monitor.probes)
phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"),
self.platform.request("urukul_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
pads = platform.request("urukul_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_dio("eem0"))
platform.add_extension(_dio("eem1"))
platform.add_extension(_dio("eem2"))
platform.add_extension(_novogorny("eem3"))
platform.add_extension(_urukul("eem5", "eem4"))
platform.add_extension(_urukul("eem6"))
platform.add_extension(_zotino("eem7"))
# EEM clock fan-out from Si5324, not MMCX
try:
self.comb += platform.request("clk_sel").eq(1)
except ConstraintError:
pass
rtio_channels = []
for i in range(24):
eem, port = divmod(i, 8)
pads = platform.request("eem{}".format(eem), port)
if i < 4:
cls = ttl_serdes_7series.InOut_8X
else:
cls = ttl_serdes_7series.Output_8X
phy = cls(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM3: Novogorny
phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"),
self.platform.request("eem3_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
for signal in "conv".split():
pads = platform.request("eem3_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM5 + EEM4: Urukul
phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
self.platform.request("eem5_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem5_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem5_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM6: Urukul
phy = spi2.SPIMaster(self.platform.request("eem6_spi_p"),
self.platform.request("eem6_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "io_update".split():
pads = platform.request("eem6_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
pads = platform.request("eem6_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
# EEM7: Zotino
phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
self.platform.request("eem7_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "ldac_n clr_n".split():
pads = platform.request("eem7_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def add_std(cls,
target,
eems_sampler,
eems_urukul,
t_rtt=4,
clk=1,
shift=11,
profile=5,
iostandard="LVDS_25"):
"""Add a 8-channel Sampler-Urukul Servo
:param t_rtt: upper estimate for clock round-trip propagation time from
``sck`` at the FPGA to ``clkout`` at the FPGA, measured in RTIO
coarse cycles (default: 4). This is the sum of the round-trip
cabling delay and the 8 ns max propagation delay on Sampler (ADC
and LVDS drivers). Increasing ``t_rtt`` increases servo latency.
With all other parameters at their default values, ``t_rtt`` values
above 4 also increase the servo period (reduce servo bandwidth).
:param clk: DDS SPI clock cycle half-width in RTIO coarse cycles
(default: 1)
:param shift: fixed-point scaling factor for IIR coefficients
(default: 11)
:param profile: log2 of the number of profiles for each DDS channel
(default: 5)
"""
cls.add_extension(target,
*(eems_sampler + sum(eems_urukul, [])),
iostandard=iostandard)
eem_sampler = "sampler{}".format(eems_sampler[0])
eem_urukul = ["urukul{}".format(i[0]) for i in eems_urukul]
sampler_pads = servo_pads.SamplerPads(target.platform, eem_sampler)
urukul_pads = servo_pads.UrukulPads(target.platform, *eem_urukul)
target.submodules += sampler_pads, urukul_pads
# timings in units of RTIO coarse period
adc_p = servo.ADCParams(
width=16,
channels=8,
lanes=4,
t_cnvh=4,
# account for SCK DDR to CONV latency
# difference (4 cycles measured)
t_conv=57 - 4,
t_rtt=t_rtt + 4)
iir_p = servo.IIRWidths(state=25,
coeff=18,
adc=16,
asf=14,
word=16,
accu=48,
shift=shift,
channel=3,
profile=profile,
dly=8)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels,
clk=clk)
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
su = ClockDomainsRenamer("rio_phy")(su)
# explicitly name the servo submodule to enable the migen namer to derive
# a name for the adc return clock domain
setattr(target.submodules, "suservo_eem{}".format(eems_sampler[0]), su)
ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
target.submodules += ctrls
target.rtio_channels.extend(
rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
mem = rtservo.RTServoMem(iir_p, su)
target.submodules += mem
target.rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
phy = spi2.SPIMaster(
target.platform.request("{}_pgia_spi_p".format(eem_sampler)),
target.platform.request("{}_pgia_spi_n".format(eem_sampler)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(2):
if len(eem_urukul) > i:
spi_p, spi_n = (target.platform.request("{}_spi_p".format(
eem_urukul[i])),
target.platform.request("{}_spi_n".format(
eem_urukul[i])))
else: # create a dummy bus
spi_p = Record([("clk", 1), ("cs_n", 1)]) # mosi, cs_n
spi_n = None
phy = spi2.SPIMaster(spi_p, spi_n)
target.submodules += phy
target.rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=4))
for j, eem_urukuli in enumerate(eem_urukul):
pads = target.platform.request(
"{}_dds_reset_sync_in".format(eem_urukuli))
target.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = target.platform.request("{}_{}".format(
eem_urukuli, signal))
target.specials += DifferentialOutput(
su.iir.ctrl[j * 4 + i].en_out, pads.p, pads.n)
def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.1"
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX
self.comb += self.platform.request("clk_sel").eq(1)
self.rtio_channels = []
# EEM0, EEM1: DIO
eem.DIO.add_std(self, 0,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
eem.DIO.add_std(self, 1,
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
# EEM3, EEM2: Sampler
self.platform.add_extension(eem.Sampler.io(3, 2))
sampler_pads = servo_pads.SamplerPads(self.platform, "sampler3")
# EEM5, EEM4 and EEM7, EEM6: Urukul
self.platform.add_extension(eem.Urukul.io_qspi(5, 4))
self.platform.add_extension(eem.Urukul.io_qspi(7, 6))
urukul_pads = servo_pads.UrukulPads(self.platform,
"urukul5", "urukul7")
adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
# account for SCK pipeline latency
t_conv=57 - 4, t_rtt=4 + 4)
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
accu=48, shift=11, channel=3, profile=5)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels, clk=1)
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
su = ClockDomainsRenamer("rio_phy")(su)
self.submodules += sampler_pads, urukul_pads, su
ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
self.submodules += ctrls
self.rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
mem = rtservo.RTServoMem(iir_p, su)
self.submodules += mem
self.rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
# EEM3: Sampler
phy = spi2.SPIMaster(self.platform.request("sampler3_pgia_spi_p"),
self.platform.request("sampler3_pgia_spi_n"))
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
# EEM5 + EEM4: Urukul
phy = spi2.SPIMaster(self.platform.request("urukul5_spi_p"),
self.platform.request("urukul5_spi_n"))
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = self.platform.request("urukul5_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = self.platform.request("urukul5_{}".format(signal))
self.specials += DifferentialOutput(
su.iir.ctrl[i].en_out,
pads.p, pads.n)
# EEM7 + EEM6: Urukul
phy = spi2.SPIMaster(self.platform.request("urukul7_spi_p"),
self.platform.request("urukul7_spi_n"))
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = self.platform.request("urukul7_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = self.platform.request("urukul7_{}".format(signal))
self.specials += DifferentialOutput(
su.iir.ctrl[i + 4].en_out,
pads.p, pads.n)
for i in (1, 2):
sfp_ctl = self.platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels)
self.platform.add_false_path_constraints(
sampler_pads.clkout_p,
self.rtio_crg.cd_rtio.clk)
self.platform.add_false_path_constraints(
sampler_pads.clkout_p,
self.crg.cd_sys.clk)
def add_std(cls,
target,
eems_sampler,
eems_urukul0,
eems_urukul1,
t_rtt=4,
clk=1,
shift=11,
profile=5):
"""Add a 8-channel Sampler-Urukul Servo
:param t_rtt: upper estimate for clock round-trip propagation time from
``sck`` at the FPGA to ``clkout`` at the FPGA, measured in RTIO
coarse cycles (default: 4). This is the sum of the round-trip
cabling delay and the 8 ns max propagation delay on Sampler (ADC
and LVDS drivers). Increasing ``t_rtt`` increases servo latency.
With all other parameters at their default values, ``t_rtt`` values
above 4 also increase the servo period (reduce servo bandwidth).
:param clk: DDS SPI clock cycle half-width in RTIO coarse cycles
(default: 1)
:param shift: fixed-point scaling factor for IIR coefficients
(default: 11)
:param profile: log2 of the number of profiles for each DDS channel
(default: 5)
"""
cls.add_extension(target,
*(eems_sampler + eems_urukul0 + eems_urukul1))
eem_sampler = "sampler{}".format(eems_sampler[0])
eem_urukul0 = "urukul{}".format(eems_urukul0[0])
eem_urukul1 = "urukul{}".format(eems_urukul1[0])
sampler_pads = servo_pads.SamplerPads(target.platform, eem_sampler)
urukul_pads = servo_pads.UrukulPads(target.platform, eem_urukul0,
eem_urukul1)
# timings in units of RTIO coarse period
adc_p = servo.ADCParams(
width=16,
channels=8,
lanes=4,
t_cnvh=4,
# account for SCK DDR to CONV latency
# difference (4 cycles measured)
t_conv=57 - 4,
t_rtt=t_rtt + 4)
iir_p = servo.IIRWidths(state=25,
coeff=18,
adc=16,
asf=14,
word=16,
accu=48,
shift=shift,
channel=3,
profile=profile)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels,
clk=clk)
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
su = ClockDomainsRenamer("rio_phy")(su)
target.submodules += sampler_pads, urukul_pads, su
ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
target.submodules += ctrls
target.rtio_channels.extend(
rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
mem = rtservo.RTServoMem(iir_p, su)
target.submodules += mem
target.rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
phy = spi2.SPIMaster(
target.platform.request("{}_pgia_spi_p".format(eem_sampler)),
target.platform.request("{}_pgia_spi_n".format(eem_sampler)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
phy = spi2.SPIMaster(
target.platform.request("{}_spi_p".format(eem_urukul0)),
target.platform.request("{}_spi_n".format(eem_urukul0)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request("{}_dds_reset".format(eem_urukul0))
target.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = target.platform.request("{}_{}".format(eem_urukul0, signal))
target.specials += DifferentialOutput(su.iir.ctrl[i].en_out,
pads.p, pads.n)
phy = spi2.SPIMaster(
target.platform.request("{}_spi_p".format(eem_urukul1)),
target.platform.request("{}_spi_n".format(eem_urukul1)))
target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request("{}_dds_reset".format(eem_urukul1))
target.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = target.platform.request("{}_{}".format(eem_urukul1, signal))
target.specials += DifferentialOutput(su.iir.ctrl[i + 4].en_out,
pads.p, pads.n)
def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.1"
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_dio("eem0"))
platform.add_extension(_dio("eem1"))
platform.add_extension(_sampler("eem3", "eem2"))
platform.add_extension(_urukul_qspi("eem5", "eem4"))
platform.add_extension(_urukul_qspi("eem7", "eem6"))
try:
# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
self.comb += platform.request("clk_sel").eq(1)
except ConstraintError:
pass
rtio_channels = []
for i in range(16):
eem, port = divmod(i, 8)
pads = platform.request("eem{}".format(eem), port)
if i < 4:
cls = ttl_serdes_7series.InOut_8X
else:
cls = ttl_serdes_7series.Output_8X
phy = cls(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM3, EEM2: Sampler
sampler_pads = servo_pads.SamplerPads(self.platform, "eem3")
# EEM5, EEM4 and EEM7, EEM6: Urukul
urukul_pads = servo_pads.UrukulPads(self.platform, "eem5", "eem7")
adc_p = servo.ADCParams(
width=16,
channels=8,
lanes=4,
t_cnvh=4,
# account for SCK pipeline latency
t_conv=57 - 4,
t_rtt=4 + 4)
iir_p = servo.IIRWidths(state=25,
coeff=18,
adc=16,
asf=14,
word=16,
accu=48,
shift=11,
channel=3,
profile=5)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels,
clk=1)
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
su = ClockDomainsRenamer("rio_phy")(su)
self.submodules += sampler_pads, urukul_pads, su
ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
self.submodules += ctrls
rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
mem = rtservo.RTServoMem(iir_p, su)
self.submodules += mem
rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
# EEM3: Sampler
phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
self.platform.request("eem3_pgia_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
# EEM5 + EEM4: Urukul
phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
self.platform.request("eem5_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem5_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = platform.request("eem5_{}".format(signal))
self.specials += DifferentialOutput(su.iir.ctrl[i].en_out, pads.p,
pads.n)
# EEM7 + EEM6: Urukul
phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
self.platform.request("eem7_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem7_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
pads = platform.request("eem7_{}".format(signal))
self.specials += DifferentialOutput(su.iir.ctrl[i + 4].en_out,
pads.p, pads.n)
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
platform.add_false_path_constraints(sampler_pads.clkout_p,
self.rtio_crg.cd_rtio.clk)
platform.add_false_path_constraints(sampler_pads.clkout_p,
self.crg.cd_sys.clk)
