def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.add_local_interface_template(AXIMasterExternal()) toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Master.vhd" module.files = [] module.dependencies = [] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "IO Infrastructure" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) internal_memory = module.get_interface("out") internal_memory.to_external = False internal_memory.instantiate_in_top = None module.get_generic("C_M_AXI_DATA_WIDTH").set_value(None) module.get_generic("C_M_AXI_ADDR_WIDTH").set_value(None) module.brief_description = "AXI Master interface. Usually automatically inserted by Automatics. Contains Xilinx-specific HDL code!" return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.files = ["hardware/hdl/vhdl/pkg/as_generic_filter_pkg.vhd"] module.dependencies = [] # As this is not a typical Automatics module (no VHDL entity) # we manually set the necessary attributes, # so Automatics can work with it normally module.module_dir = module_dir module.repository_name = "default" module.name = "as_generic_filter" module.entity_name = "as_generic_filter" module.generics = [] module.standard_ports = [] module.ports = [] module.interfaces = [] # Automatic module discovery would run into errors (no entity in 'as_generic_filter_pkg') # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces #module.discover_module("{mdir}/{toplevel}" # .format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_canny_pipeline.vhd" module.files = [] module.dependencies = [ "as_regmgr", "as_generic_filter_module", "as_pipeline_flush", "as_edge_threshold", "as_edge_nms", "as_cordic_direction", "as_gradient_weight", "as_edge_list", "as_feature_counter", "helpers", "as_2d_conv_filter_internal", "as_pipeline_row", "as_window_pipeline_helper", ] module.show_in_browser = True module.dev_status = AsModule.DevStatus.BETA module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "Image Processing Pipeline" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hdl/vhdl/as_gensync.vhd" module.files = [] module.dependencies = [] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/hardware/{toplevel}".format( mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir): module = AsModule("as_myfilter_new") toplevel_file = "hardware/hdl/vhdl/as_myfilter_new.vhd" module.files = [] module.dependencies = ["helpers"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}" .format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_gauss.vhd" module.dependencies = ["as_regmgr", "as_window_buff_nxm", "as_generic_filter_module", "as_pipeline_flush"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}" .format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_sensor_ov7670.vhd" module.files = [] module.dependencies = ["as_regmgr"] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "External IO" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) module.iic_masters = [] module.iic_masters_available = ("XILINX_PL_IIC", "XILINX_PS_IIC", "AS_IIC") # Special function definitions for as_sensor_ov7670 module: def add_iic_master(self, iic_type: str): self.iic_masters.append(iic_type) LOG.info("Added IIC master '%s' to '%s'", iic_type, self.name) def set_iic_masters(self, iic_types: list): self.iic_masters = iic_types def list_iic_masters(self): print("IIC masters available for '{}':".format(self.name)) for iic in self.iic_masters_available: print(" - '{}'".format(iic)) print("") def overwrite_sw_additions(self) -> list: additions = [] for master in self.iic_masters: additions.append("#define AS_USING_{}".format(master.upper())) return additions # Assign functions to module instance # The call to "__get__(module)" is necessary and "binds" the method # the instance AsModule instance "module" that was created here! # Syntax: # module.<function_name (user script)> = <function to add>.__get__(module) module.set_iic_masters = set_iic_masters.__get__(module) module.add_iic_master = add_iic_master.__get__(module) module.list_iic_masters = list_iic_masters.__get__(module) module.get_software_additions = overwrite_sw_additions.__get__(module) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_memwriter.vhd" module.files = ["hardware/hdl/vhdl/as_mem_address_generator.vhd"] module.dependencies = ["as_regmgr", "helpers", "fifo_fwft"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_iic.vhd" module.files = [] module.dependencies = ["helpers", "as_regmgr"] module.add_local_interface_template(IIC_Interface()) # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/fifo/fifo_fwft.vhd" module.files = [] module.dependencies = ["helpers", "ram"] module.show_in_browser = False module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "Internal Submodules" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir): module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_base_registers.vhd" module.dependencies = ["as_regmgr"] module.show_in_browser = False module.dev_status = AsModule.DevStatus.WORK_IN_PROGRESS module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "ASTERICS Infrastructure" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_pixel_conv.vhd" module.dependencies = [] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "Image Processing Operations" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_stream_adapter.vhd" module.files = [] module.dependencies = ["helpers"] module.dev_status = AsModule.DevStatus.BETA module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "As Stream Infrastructure" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_mux.vhd" module.dependencies = [] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file)) sel_reg = module.get_port("sel_reg") sel_reg.set_port_type("external") sel_reg.add_rule("external_port", "make_external") return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_memwriter.vhd" module.files = ["hardware/hdl/vhdl/as_mem_address_generator.vhd"] module.dependencies = ["as_regmgr", "helpers", "fifo_fwft"] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "Memory IO" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_channel_splitter_3.vhd" module.files = [] module.dependencies = [] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "As Stream Infrastructure" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_picam.vhd" module.files = [] module.dependencies = ["as_regmgr"] module.show_in_browser = True module.dev_status = AsModule.DevStatus.ALPHA module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "External IO" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_stream_strobe_counter.vhd" module.files = [] module.dependencies = [] module.show_in_browser = True module.dev_status = AsModule.DevStatus.BETA module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "Debugging Modules" # Automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.add_local_interface_template(SWRegInterface()) toplevel_file = "hardware/hdl/vhdl/register_interface/as_regmgr.vhd" module.files = [("hardware/hdl/vhdl/register_interface/" "as_generic_regslice.vhd")] module.dependencies = ["helpers"] module.show_in_browser = False module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "Internal Submodules" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) # Configuration method. This method is automatically executed # by Automatics during the connection process, only if the module was # automatically instantiated. # This way we can access information only available at runtime. def auto_inst_config(mod, inst_from): # inst_from is the module that automatically instantiated this module # mod is the instance of this module that was automatically instantiated mod.set_generic_value("REG_ADDR_WIDTH", "c_slave_reg_addr_width") mod.set_generic_value("REG_DATA_WIDTH", "C_S_AXI_DATA_WIDTH") mod.set_generic_value("MODULE_ADDR_WIDTH", "c_module_addr_width") base_addr_generic = vstatic.REGMGR_BASEADDR_VAL.format(inst_from.name) mod.set_generic_value("MODULE_BASEADDR", base_addr_generic) regmgr_count = "_" + mod.name[-1] if mod.name[-1].isdigit() else "" target = vstatic.REGMGR_SW_DATA_OUT_TARGET.format( inst_from.name, regmgr_count) mod.set_port_fixed_value("sw_data_out", target) if not regmgr_count: regif = inst_from.register_ifs[0] else: regif = inst_from.register_ifs[int(regmgr_count.strip("_"))] mod.set_generic_value("REG_COUNT", str(regif.get_reg_count())) mod.get_interface("out", if_type="slv_reg_interface").to_external = False # !Important! Assign the configuration function to this module instance module.auto_inst_config = auto_inst_config # Return the module instance to Automatics return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.add_local_interface_template(AXISlaveExternal()) toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd" module.files = [] module.dependencies = ["fifo_fwft", "helpers"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file)) module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None) module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() toplevel_file = "hardware/hdl/vhdl/as_single_conv_filter.vhd" module.dependencies = [ "as_regmgr", "as_window_buff_nxm", "as_generic_filter_module", "as_pipeline_flush", ] module.show_in_browser = True module.dev_status = AsModule.DevStatus.UNMAINTAINED module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL module.module_category = "Image Processing Operations" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.files = ["hardware/hdl/vhdl/pkg/helpers.vhd"] module.dependencies = [] # As this is not a typical Automatics module (no VHDL entity) # we manually set the necessary attributes, # so Automatics can work with it normally module.module_dir = module_dir module.repository_name = "default" module.name = "" module.entity_name = "helpers" module.generics = [] module.standard_ports = [] module.ports = [] module.interfaces = [] module.show_in_browser = False module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.LIBRARY module.module_category = "Internal Libraries" return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.files = [] module.dependencies = [] # As this is not a typical Automatics module (no HW files) # we manually set the necessary attributes, # so Automatics can work with it module.module_dir = module_dir module.repository_name = "default" module.name = "as_memio" module.entity_name = "as_memio" module.generics = [] module.standard_ports = [] module.ports = [] module.interfaces = [] module.show_in_browser = False module.dev_status = AsModule.DevStatus.BETA module.module_type = AsModule.ModuleTypes.SOFTWARE module.module_category = "Memory IO" return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.files = ["hardware/hdl/vhdl/pkg/helpers.vhd"] module.dependencies = [] # As this is not a typical Automatics module (no VHDL entity) # we manually set the necessary attributes, # so Automatics can work with it normally module.module_dir = module_dir module.repository_name = "default" module.name = "" module.entity_name = "helpers" module.generics = [] module.standard_ports = [] module.ports = [] module.interfaces = [] # Automatic module discovery would run into errors (no entity in 'helpers') #module.discover_module("{mdir}/{toplevel}" # .format(mdir=module_dir, toplevel=toplevel_file)) return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.add_local_interface_template(SimReaderRegisterInterface()) toplevel_file = "hardware/hdl/vhdl/sim/as_sim_file_reader.vhd" module.files = [] module.dependencies = ["as_sim_ram_pkg", "helpers"] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE_SOFTWARE module.module_category = "Simulation Resources" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) module.driver_files = [ "hardware/hdl/vhdl/sim/read_byte.h", "hardware/hdl/vhdl/sim/read_byte.c", ] return module
def get_module_instance(module_dir: str) -> AsModule: module = AsModule() module.add_local_interface_template(AXISlaveExternal()) toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd" module.files = [] module.dependencies = ["fifo_fwft", "helpers"] module.show_in_browser = True module.dev_status = AsModule.DevStatus.STABLE module.module_type = AsModule.ModuleTypes.HARDWARE module.module_category = "IO Infrastructure" # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module(module_dir + "/" + toplevel_file) module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None) module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None) module.brief_description = ( "AXI Slave interface. Usually automatically inserted by Automatics.") return module
def get_module_instance(module_dir: str) -> AsModule: # Instantiate 'module' as a new ASTERICS module module = AsModule() # Pre-Discovery configuration: # Here, certain configuration options can be used: # Add a custom interface template, defined above, as a possible interface # of this module: # module.add_local_interface_template(<InterfaceClass>()) # Here the toplevel file for the module has to be defined. # Example, for the file: # "modules/as_memwriter/hardware/hdl/vhdl/writer/as_memwriter.vhd" # The path to spedify is: "hdl/vhdl/writer/as_memwriter.vhd" toplevel_file = "path/to/toplevel/toplevel_filename.vhd" # Here all other required files in the module's folder need to be specified. # The search path starts at the module's folder, as with the toplevel. module.files = [ "hardware/hdl/vhdl/common_file.vhd", "hardware/hdl/vhdl/library.vhd", "hardware/hdl/vhdl/extra_component.vhd", "hardware/hdl/verilog/vendor_lib.v", "hardware/hdl/vhdl/subfolder/shared_component.vhd", ] # If this module uses files from other modules or from a shared module # such as the files in the "as_misc" folder (not technically a module), # these have to be declared here. # Only the module name has to be listed here # (not the folder name, the module name!). module.dependencies = ["as_memwriter", "as_lib", "helpers"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module( "{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file) ) # Custom Interfaces: # Your module may implement a new interface that the generator could # manage automatically. There are two places where you can specify a new # Interface: In this file, above the definition of the function # "get_module_instance", or in the user script. # To add the defined interface to Automatics, you may use one of two methods # Use: 'AsModule.add_global_interface_template(InterfaceClassName())' # for interfaces used in more than one module. # If the interface is exclusive to this or very few modules, use: # 'module.add_local_interface_template(InterfaceClassName()) # in every module witht the interface. # Module configuration: # Here you can add/modify configuration parameters for interfaces, generics, # ports, register interfaces and the module itself. # Here is a list of possible configuration options along with a brief # explanation of what they do. For more detailed information, check # the chapter about Automatics in the ASTERICS manual. # Rules for ports: # Ports need to be assigned rules. # These rules tell Automatics what to do with the ports when it # comes time to build a system. When the generator integrates a module # into a system it will match up interfaces of modules and their ports. # Depending on the condition, which ports are available, Automatics # needs to choose which rules to follow. # Valid rule conditions: # Conditions for comparing two ports of interfaces: # - "any_present" (this is always true) # - "both_present" # - "sink_missing" # Conditions for ports not part of an interface: # - "single_port" # - "external_port" # Valid rule-actions: # "connect": # Only applicable on the condition "both_present". # Connects the two ports to each other # "make_external": # Only applicable on the condition "single_port" or "external_port". # The generator will connect the port through to the toplevel # of the ASTERICS IP-Core. # "error" # Applicable for any condition. # Raises an error message and stops as_automatics. # "warning" # Applicable for any condition. # Prints a warning message, continuing the process. # "note" # Applicable for any condition. # Prints a n information message to the console output and build log. # "set_value(<value>)" # Applicable to the conditions "single_port", # "sink_missing", "any_present". # Sets the port to the user defined <value>. # This can be a VHDL signal name, VHDL keyword, # number or data representation (eg. '1', X"F00BA5", open, reg_03). # The "value" given will be directly copied into the VHDL source code. # "bundle_and" # Applicable to all conditions. # Similar to "make_external", but bundles all ports with the same # rule and name of all ASTERICS modules in this system. # The signals are bundled together using a single big AND gate. # "bundle_or" # This rule behaves exactly like "bundle_and", except that for # this rule the signals are bundled using a big OR gate. # "fallback_port(<port name>)" # Applicable to "sink_missing", # depending on the ports data direction. # This action defines another port the port may be connected to, if its # counterpart is missing. # "none" # The default rule action: Do nothing. # By default all ports are assigned a minimal ruleset: # 1. "both_present" -> "connect" # 2. "sink_missing" -> "note" # Use the following functions to modify the rulesets of ports to fit # your needs: # Use this line to add a rule to a port, one rule action at a time. # module.port_rule_add("<Port name>", "<rule_condition>", "<rule_action>") # Use this line to replace all rule actions for a single condition with # a new rule action. # module.port_rule_overwrite("<Port name>", "<rule_condition>", # "<new_rule_action>") # Use this line to remove a rule condition from a port # module.port_rule_remove("<Port name>", "<rule_condition>") # Use this line to remove all rules from a port # module.get("<Port Name>").set_ruleset([]) # More configuration functions: # Configure generics: # "to_external"-attribute: Default value is "False", setting this to "True" # will cause Automatics to propagate this Generic to toplevel, if no # value is set in the user script. # module.make_generic_external("<generic name>") # "link_to"-attribute: The generic will be set to the generic provided. # Automatics will search each higher level module for matching generics. # Using this attribute you can set a custom generic to any of the external # or standard toplevel generics (such as AXI specific generics). # module.link_generic("<generic name>", "<generic to link to>") # You can define a function that is used to check the values the generic # is "allowed" to take on: # module.get_generic(<Generic name>).set_value_check(<function>) # The function can be any Python function that takes one value and returns # True or False. It is recommended to use lambda expressions for brevity # Example: Allow only values between 16 and 256 for generic "DIN_WIDTH" # func = lambda value: (value > 15) and (value < 257) # module.get_generic("DIN_WIDTH").set_value_check(func) # This function will check the value that # the generic is set to in the user script. # In case you want to have your module automatically instantiated, you have # the option to define an additional configuration function here, that is # run only if this module is added by way of automatic instantiation. # This has the benefit that at the time the function is run, additional # information is available, most noteably the object of the instantiating # module. Furthermore, the function is run after all user specified # connection methods have been run - the processing system is mostly # built already. # Here is an example definition of the configuration function - for a real # use case example, see the specification file of the as_regmgr module in # "modules/as_misc/hardware/automatics/as_regmgr_spec.py" # # def auto_inst_config(this_module, instantiated_from): # # Add first Generic of instantiating module to this module # this_module.set_generic(instantiated_from.generics[0]) return module
def get_module_instance(module_dir: str) -> AsModule: # In this line the generic module data is set up. # Enter the module name in the parenthenses. # (By convention it should match the name of the toplevel VHDL file): module = AsModule() # Pre-Discovery configuration: # Here, certain configuration options can be used: # Add a custom interface template, defined above, as a possible interface # of this module: # module.add_local_interface_template(<InterfaceClass>()) # TODO # Here the toplevel file for the module has to be defined. # Example, for the file: # "modules/as_memwriter/hardware/hdl/vhdl/writer/as_memwriter.vhd" # The path to spedify is: "hdl/vhdl/writer/as_memwriter.vhd" toplevel_file = "hardware/vhdl/as_myfilter.vhd" # Here all other required files in the module's folder need to be specified. # The search path starts at the module top-folder, as with the toplevel. module.files = [] # If this module uses files from other modules or from a shared module # such as the files in the "as_misc" folder (not technically a module), # these have to be declared here. # Only the module name has to be listed here # (not the folder name, the module name!). module.dependencies = ["helpers"] # as_automatics now automatically parses the toplevel file and discovers # ports, generics, existing interfaces and register interfaces module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir, toplevel=toplevel_file)) # Special Interfaces: # Your module may implement a new interface that the generator could # manage automatically. There are two places where you can specify new # Interface: In this file, above the definition of the function # "get_module_instance", or # Module configuration: # Here you can add configuration parameters for interfaces, generics, # ports, register interfaces and the module itself. # Here is a list o possible configuration options along with a brief # explanation of what they do. For more detailed information, check # the chapter about as_automatics in the ASTERICS manual. # Rules for ports: # Ports need to be assigned rules. # These rules tell the generator what to do with the ports when it # comes time to build a system. When the generator integrates a module # into a system it will match up interfaces of modules and their ports. # Depending on the condition, which ports are available, the generator # needs to choose which rules to follow. # Valid rule conditions: # Conditions for comparing two ports of interfaces: # - "any_missing" # - "any_present" # - "both_missing" # - "both_present" # - "sink_present" # - "sink_missing" # - "source_present" # - "source_missing" # Conditions for ports not part of an interface: # - "single_port" # - "external_port" # Valid rule-actions: # "connect": # Only applicable on the condition "both_present". # Connects the two ports to each other # "make_external": # Only applicable on the condition "single_port". # The generator will connect the port through to the toplevel # of the ASTERICS IP-Core, keeping the original name of the port # "error" # Applicable for any condition. # Raises an error message and stops as_automatics. # "warning" # Applicable for any condition. # Raises a warning message and halts as_automatics, # waiting for user input. # "note" # Applicable for any condition. # Prints an note to the console output and build logs. # "set_value(<value>)" # Applicable to the conditions "any_missing", "single_port", # "sink_missing" and "source_missing". # Sets the port to the user defined <value>. # This can be a VHDL signal name, VHDL keyword, # number or data representation (eg. '1', X"F00BA5", open, reg_03). # The "value" given will be directly copied into the VHDL source code. # "bundle_and" # Applicable to all conditions except for "both_missing", # "source_missing" and "any_missing" # Similar to "make_external", but bundles all ports with the same # rule and name of all ASTERICS modules in this system. # The signals are bundled together using a single big AND gate. # "bundle_or" # This rule behaves exactly like "bundle_and", exceept that for # this rule the signals are bundled using a big OR gate. # "fallback_port(<port name>)" # This action defines another port the port may be connected to, if its # counterpart is missing. # "none" # The default rule action: Do nothing. Basically a placeholder. # By default all ports are assigned a minimal ruleset: # 1. "both_present" -> "connect" # 2. "sink_missing" -> "warning" # Use the following functions to modify the rulesets of ports to fit # your needs: # Use this line to add a rule to a port, one rule action at a time. # module.get_port("<Port name>").add_rule("<rule_condition>", "<rule_action>") # Use this line to replace all rule actions for a single condition with # a new rule action. # module.get_port("<Port name>").overwrite_rule("<rule_condition>", "<new_rule_action>") # Use this line to remove a rule condition from a port # module.get_port("<Port name>").remove_rule("<rule_condition>") # More configuration functions: # Configure generics: # "to_external"-attribute: If you set this attribute to "True", the generic # will be propagated to the top-level of the ASTERICS ip-core. #module.get_generic("<generic_name>").to_external = True # "link_to"-attribute: The generic will be set to the generic provided. # The generator will search each higher level file for matching generics. # Using this attribute you can set a custom generic to any of the external # or standard toplevel generics (such as AXI specific generics). # This attribute supports wildcard characters: # '?' for single characters, '*' for multiple characters #module.get_generic("<generic name>").link_to = "<generic to link to>" # You can define a function that is used to check the values the generic # is "allowed" to take on: # module.get_generic(<Generic name>).set_value_check(<function>) # The function can be any Python function that takes one value and returns # True or False. It is recommended to use lambda expressions for brevity # Example: Allow only values between 16 and 256 for generic "DIN_WIDTH" #func = lambda value: (value > 15) and (value < 257) # module.get_generic("DIN_WIDTH").set_value_check(func) # Example: Allow only the values 16, 32, 48 and 64 for generic "BUS_WIDTH" #func = lambda value: value in (16, 32, 48, 64) # module.get_generic("BUS_WIDTH").set_value_check(func) # TODO return module