def view(self):
'''
Helper method; prints out a simple display of CPU state.
'''
kw = self.__dict__.copy()
kw['A'] = self.R[self.ira]
print '- ' * 40
print 'PC: [0x%(PC)04x] = 0x%(IR)08x =' % kw, dis(int(self.IR))
print
if self.STR:
print 'Storing', '[0x%(addr)04x] <- R%(ira)i = 0x%(A)08x' % kw
print
elif self.LDR:
print 'loading', 'R%(ira)i <- [0x%(addr)04x]' % kw
print
for i in range(0, 16, 2):
reg0, reg1 = self.R[i], self.R[i + 1]
print 'R%-2i = 0x%-8x' % (i + 1, reg1),
print 'R%-2i = 0x%-8x' % (i, reg0)
print
def view(self):
'''
Helper method; prints out a simple display of CPU state.
'''
kw = self.__dict__.copy()
kw['A'] = self.R[self.ira]
print '- ' * 40
print 'PC: [0x%(PC)04x] = 0x%(IR)08x =' % kw, dis(int(self.IR))
print
if self.STR:
print 'Storing', '[0x%(addr)04x] <- R%(ira)i = 0x%(A)08x' % kw
print
elif self.LDR:
print 'loading', 'R%(ira)i <- [0x%(addr)04x]' % kw
print
for i in range(0, 16, 2):
reg0, reg1 = self.R[i], self.R[i + 1]
print 'R%-2i = 0x%-8x' % (i + 1, reg1),
print 'R%-2i = 0x%-8x' % (i, reg0)
print
01000000110110000000001000011100
01000001000000000000000000000101
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001111011
11110111111111111111111001100110
10001101000000000000000000000111
01000000110110000000001000100100
01000001000000000000000000000100
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001110000
11110111111111111111111001011111
10001101000000000000000000000111
01000000110110000000001000101000
01000001000000000000000000000100
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001100110
11110111111111111111111001011000
10001111111000000000000000000000
01001110111010000000000000000100
11000111000000000000000000001111'''.split()
]
if __name__ == '__main__':
from assembler import dis
for i, n in enumerate(data):
## print '0x%08x' % i, dis(n)
print dis(n)
Mov_imm(1, 7), # 01: Mov R1 <- 7
Add(1, 1, 8), # 02: Add R1 <- R1 + R8
Mov_imm(2, -2), # 03: Mov R2 <- -2
Add(1, 1, 2), # 04: Add R1 <- R1 + R2
Lsl_imm(1, 1, 2), # 05: Lsl R1 <- R1 << 2
T_link(1), # 06: BR to R1 (infinite loop)
# At this point in execution R1 contains 24 (0x18) which is divided
# by 4 (bytes per instruction) giving RAM address 6, so the RISC
# emulator enters an infinite loop.
)):
memory.put(addr * 4, int(instruction))
# Print out a view of the program in RAM.
for address in sorted(memory.store):
instruction = memory[address * 4]
print('%02i: '
'%10i '
'0x%08x '
'%s') % (
address,
instruction,
instruction,
_format_bin(instruction),
), dis(instruction)
risc_cpu = RISC(memory)
for _ in range(10):
risc_cpu.cycle()
risc_cpu.view()
0xC700000F, 0x4EE90014, 0xAFE00000, 0x60000008,
0x40060004, 0xA0E00004, 0x80E00004, 0x41000000,
0xF7FFFFBF, 0x40000010, 0x80000000, 0xA0E00010,
0x80E00004, 0x40080001, 0xA0E00004, 0x40000200,
0xA0E00008, 0x80E00008, 0x81E00010, 0x00090001,
0xED00000A, 0x80E00004, 0x81E00008, 0xF7FFFFB0,
0x80E00004, 0x40080001, 0xA0E00004, 0x80E00008,
0x40080200, 0xA0E00008, 0xE7FFFFF2, 0x8FE00000,
0x4EE80014, 0xC700000F, 0x4D000000, 0x5E00FFC0,
0x6E000008, 0x4C000020, 0x0000000F, 0x40090000,
0xE9000012, 0x40000080, 0x5100FFC4, 0xA0100000,
0xF7FFFF50, 0x5000FFC4, 0x80000000, 0x40030001,
0xE8000005, 0x40000081, 0x5100FFC4, 0xA0100000,
0xF7FFFEC1, 0xE7000004, 0x40000082, 0x5100FFC4,
0xA0100000, 0xF7FFFFC7, 0xE7000008, 0x5000FFC4,
0x80000000, 0x40030001, 0xE8000004, 0x40000081,
0x5100FFC4, 0xA0100000, 0xF7FFFEB3, 0x4000000C,
0x6100000E, 0x41167EF0, 0xA1000000, 0x40000018,
0x61000008, 0xA1000000, 0x40000084, 0x5100FFC4,
0xA0100000, 0x40000000, 0xC7000000,
)
ROMStart = 0xFFFFF800 / 4
if __name__ == '__main__':
from assembler import dis
for i, instruction in enumerate(bootloader):
print '0x%08x - 0x%04x : %s' % (i + ROMStart, i, dis(instruction))
Lsl_imm(1, 1, 2), # 05: Lsl R1 <- R1 << 2
T_link(1), # 06: BR to R1 (infinite loop)
# At this point in execution R1 contains 24 (0x18) which is divided
# by 4 (bytes per instruction) giving RAM address 6, so the RISC
# emulator enters an infinite loop.
)):
memory.put(addr * 4, int(instruction))
# Print out a view of the program in RAM.
for address in sorted(memory.store):
instruction = memory[address * 4]
print (
'%02i: '
'%10i '
'0x%08x '
'%s'
) % (
address,
instruction,
instruction,
_format_bin(instruction),
), dis(instruction)
risc_cpu = RISC(memory)
for _ in range(10):
risc_cpu.cycle()
risc_cpu.view()
01000000110110000000001000011100
01000001000000000000000000000101
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001111011
11110111111111111111111001100110
10001101000000000000000000000111
01000000110110000000001000100100
01000001000000000000000000000100
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001110000
11110111111111111111111001011111
10001101000000000000000000000111
01000000110110000000001000101000
01000001000000000000000000000100
01000010000000000000000000000110
10000011110100000000000000101000
01000100000000000000000001100110
11110111111111111111111001011000
10001111111000000000000000000000
01001110111010000000000000000100
11000111000000000000000000001111'''.split()]
if __name__ == '__main__':
from assembler import dis
for i, n in enumerate(data):
## print '0x%08x' % i, dis(n)
print dis(n)