def bench():
# Parameters
AXI_DATA_WIDTH = 32
AXI_ADDR_WIDTH = 16
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 16
LEN_WIDTH = 20
TAG_WIDTH = 8
ENABLE_UNALIGNED = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_desc_read_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_desc_write_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_desc_valid = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
enable = Signal(bool(0))
# Outputs
s_axis_desc_ready = Signal(bool(0))
m_axis_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_desc_status_valid = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(2)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(0)[4:])
m_axi_awprot = Signal(intbv(0)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(2)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(0)[4:])
m_axi_arprot = Signal(intbv(0)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_pause = Signal(bool(False))
axi_ram_port0 = axi_ram_inst.create_port(clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
pause=axi_ram_pause,
name='port0')
# sources and sinks
desc_source = axis_ep.AXIStreamSource()
desc_source_pause = Signal(bool(False))
desc_source_logic = desc_source.create_logic(
clk,
rst,
tdata=(s_axis_desc_read_addr, s_axis_desc_write_addr, s_axis_desc_len,
s_axis_desc_tag),
tvalid=s_axis_desc_valid,
tready=s_axis_desc_ready,
pause=desc_source_pause,
name='desc_source')
desc_status_sink = axis_ep.AXIStreamSink()
desc_status_sink_logic = desc_status_sink.create_logic(
clk,
rst,
tdata=(m_axis_desc_status_tag, ),
tvalid=m_axis_desc_status_valid,
name='desc_status_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_desc_read_addr=s_axis_desc_read_addr,
s_axis_desc_write_addr=s_axis_desc_write_addr,
s_axis_desc_len=s_axis_desc_len,
s_axis_desc_tag=s_axis_desc_tag,
s_axis_desc_valid=s_axis_desc_valid,
s_axis_desc_ready=s_axis_desc_ready,
m_axis_desc_status_tag=m_axis_desc_status_tag,
m_axis_desc_status_valid=m_axis_desc_status_valid,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
enable=enable)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while desc_status_sink.empty():
yield clk.posedge
def wait_pause_ram():
while desc_status_sink.empty():
axi_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_ram_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
enable.next = 1
yield clk.posedge
print("test 1: transfer")
current_test.next = 1
read_addr = 0x00000000
write_addr = 0x00008000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(read_addr, test_data)
data = axi_ram_inst.read_mem(read_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
desc_source.send([(read_addr, write_addr, len(test_data), cur_tag)])
yield desc_status_sink.wait(1000)
status = desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = axi_ram_inst.read_mem(write_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(write_addr, len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 2: various transfers")
current_test.next = 2
for length in list(range(1, 17)) + [128]:
for read_offset in list(range(8, 16, 4)) + list(
range(4096 - 8, 4096, 4)):
for write_offset in list(range(8, 16, 4)) + list(
range(4096 - 8, 4096, 4)):
for wait in wait_normal, wait_pause_ram:
print("length %d, read offset %d, write offset %d" %
(length, read_offset, write_offset))
read_addr = read_offset
write_addr = 0x00008000 + write_offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(read_addr, test_data)
axi_ram_inst.write_mem(
write_addr & 0xffff80,
b'\xaa' * (len(test_data) + 256))
data = axi_ram_inst.read_mem(read_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
desc_source.send([(read_addr, write_addr,
len(test_data), cur_tag)])
yield wait()
status = desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = axi_ram_inst.read_mem(write_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(
write_addr - 8,
len(test_data) +
16) == b'\xaa' * 8 + test_data + b'\xaa' * 8
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
AXIS_PCIE_CQ_USER_WIDTH = 85
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
# Outputs
s_axis_cq_tready = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(5)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(3)[4:])
m_axi_awprot = Signal(intbv(2)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(1))
status_error_uncor = Signal(bool(0))
# Clock and Reset Interface
user_clk=Signal(bool(0))
user_reset=Signal(bool(0))
sys_clk=Signal(bool(0))
sys_reset=Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(
user_clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
name='port0'
)
# PCIe devices
rc = pcie.RootComplex()
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 250e6
dev.functions[0].configure_bar(0, 16*1024*1024)
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_cc_tuser=Signal(intbv(0)[33:]),
s_axis_cc_tlast=Signal(bool(0)),
s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_cc_tvalid=Signal(bool(0)),
s_axis_cc_tready=Signal(bool(0)),
# Requester reQuest Interface
s_axis_rq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_rq_tuser=Signal(intbv(0)[60:]),
s_axis_rq_tlast=Signal(bool(0)),
s_axis_rq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_rq_tvalid=Signal(bool(0)),
s_axis_rq_tready=Signal(bool(1)),
# pcie_rq_seq_num=pcie_rq_seq_num,
# pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_rc_tuser=Signal(intbv(0)[75:]),
m_axis_rc_tlast=Signal(bool(0)),
m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_rc_tvalid=Signal(bool(0)),
m_axis_rc_tready=Signal(bool(0)),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tvalid=s_axis_cq_tvalid,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tuser=s_axis_cq_tuser,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
status_error_uncor=status_error_uncor
)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
status_error_uncor_asserted = Signal(bool(0))
@always(user_clk.posedge)
def monitor():
if (status_error_uncor):
status_error_uncor_asserted.next = 1
cq_pause_toggle = Signal(bool(0))
cc_pause_toggle = Signal(bool(0))
rq_pause_toggle = Signal(bool(0))
rc_pause_toggle = Signal(bool(0))
@instance
def pause_toggle():
while True:
if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle or rc_pause_toggle):
cq_pause.next = cq_pause_toggle
cc_pause.next = cc_pause_toggle
rq_pause.next = rq_pause_toggle
rc_pause.next = rc_pause_toggle
yield user_clk.posedge
yield user_clk.posedge
yield user_clk.posedge
cq_pause.next = 0
cc_pause.next = 0
rq_pause.next = 0
rc_pause.next = 0
yield user_clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate()
dev_bar0 = rc.tree[0][0].bar[0]
yield delay(100)
yield clk.posedge
print("test 2: memory write")
current_test.next = 2
pcie_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
yield rc.mem_write(dev_bar0+pcie_addr, test_data)
yield delay(300)
data = axi_ram_inst.read_mem(pcie_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axi_ram_inst.read_mem(pcie_addr, len(test_data)) == test_data
assert not status_error_uncor_asserted
yield delay(100)
yield user_clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in list(range(1,34))+[1024]:
for pcie_offset in list(range(8,41))+list(range(4096-32,4096)):
for pause in [False, True]:
print("length %d, pcie_offset %d"% (length, pcie_offset))
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
pcie_addr = pcie_offset
test_data = bytearray([x%256 for x in range(length)])
axi_ram_inst.write_mem(pcie_addr & 0xffff80, b'\x55'*(len(test_data)+256))
cq_pause_toggle.next = pause
yield from rc.mem_write(dev_bar0+pcie_addr, test_data)
yield delay(int(length*4+60))
cq_pause_toggle.next = 0
data = axi_ram_inst.read_mem(pcie_addr&0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axi_ram_inst.read_mem(pcie_addr-1, len(test_data)+2) == b'\x55'+test_data+b'\x55'
assert not status_error_uncor_asserted
yield delay(100)
yield clk.posedge
print("test 4: bad request")
current_test.next = 4
try:
yield from rc.mem_read(dev_bar0, 4, 100)
except:
print("Caught timeout exception")
pass
else:
assert False
assert status_error_uncor_asserted
status_error_uncor_asserted.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_CLIENT_TAG = 1
PCIE_TAG_WIDTH = 8
PCIE_TAG_COUNT = 256
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
m_axis_rq_tready = Signal(bool(0))
s_axis_pcie_rq_tag = Signal(intbv(0)[PCIE_TAG_WIDTH:])
s_axis_pcie_rq_tag_valid = Signal(bool(0))
s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
enable = Signal(bool(0))
ext_tag_enable = Signal(bool(0))
requester_id = Signal(intbv(0)[16:])
requester_id_enable = Signal(bool(0))
max_read_request_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rc_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(5)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(3)[4:])
m_axi_awprot = Signal(intbv(2)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(user_clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
name='port0')
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_logic = read_desc_source.create_logic(
user_clk,
user_reset,
tdata=(s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr,
s_axis_read_desc_len, s_axis_read_desc_tag),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
name='read_desc_source')
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
user_clk,
user_reset,
tdata=(m_axis_read_desc_status_tag, ),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink')
# PCIe devices
rc = pcie.RootComplex()
mem_base, mem_data = rc.alloc_region(16 * 1024 * 1024)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_cq_tuser=Signal(intbv(0)[85:]),
m_axis_cq_tlast=Signal(bool(0)),
m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_cq_tvalid=Signal(bool(0)),
m_axis_cq_tready=Signal(bool(1)),
pcie_cq_np_req=Signal(bool(1)),
pcie_cq_np_req_count=Signal(intbv(0)[6:]),
# Completer Completion Interface
s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_cc_tuser=Signal(intbv(0)[33:]),
s_axis_cc_tlast=Signal(bool(0)),
s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_cc_tvalid=Signal(bool(0)),
s_axis_cc_tready=Signal(bool(0)),
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
# pcie_rq_seq_num=pcie_rq_seq_num,
# pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tuser=m_axis_rq_tuser,
s_axis_pcie_rq_tag=s_axis_pcie_rq_tag,
s_axis_pcie_rq_tag_valid=s_axis_pcie_rq_tag_valid,
s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr,
s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
enable=enable,
ext_tag_enable=ext_tag_enable,
requester_id=requester_id,
requester_id_enable=requester_id_enable,
max_read_request_size=max_read_request_size,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
status_error_cor_asserted = Signal(bool(0))
status_error_uncor_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (status_error_cor):
status_error_cor_asserted.next = 1
if (status_error_uncor):
status_error_uncor_asserted.next = 1
cq_pause_toggle = Signal(bool(0))
cc_pause_toggle = Signal(bool(0))
rq_pause_toggle = Signal(bool(0))
rc_pause_toggle = Signal(bool(0))
@instance
def pause_toggle():
while True:
if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle
or rc_pause_toggle):
cq_pause.next = cq_pause_toggle
cc_pause.next = cc_pause_toggle
rq_pause.next = rq_pause_toggle
rc_pause.next = rc_pause_toggle
yield user_clk.posedge
yield user_clk.posedge
yield user_clk.posedge
cq_pause.next = 0
cc_pause.next = 0
rq_pause.next = 0
rc_pause.next = 0
yield user_clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
max_read_request_size.next = 2
enable.next = 1
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True)
yield delay(100)
yield user_clk.posedge
print("test 2: PCIe read")
current_test.next = 2
pcie_addr = 0x00000000
axi_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
mem_data[pcie_addr:pcie_addr + len(test_data)] = test_data
data = mem_data[pcie_addr:pcie_addr + 32]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(pcie_addr, axi_addr, len(test_data), cur_tag)])
yield read_desc_status_sink.wait(2000)
yield delay(50)
status = read_desc_status_sink.recv()
print(status)
data = axi_ram_inst.read_mem(axi_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(axi_addr, len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield user_clk.posedge
print("test 3: various reads")
current_test.next = 3
for length in list(range(1, 35)) + list(range(128 - 4,
128 + 4)) + [1024]:
for pcie_offset in list(range(8, 13)) + list(
range(4096 - 4, 4096 + 4)):
for axi_offset in list(range(8, 41)) + list(
range(4096 - 32, 4096)):
for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d" %
(length, pcie_offset, axi_offset))
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
pcie_addr = pcie_offset
axi_addr = axi_offset
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr +
len(test_data)] = test_data
data = mem_data[pcie_addr
& 0xffff80:(pcie_addr & 0xffff80) + 64]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
axi_ram_inst.write_mem(
axi_addr & 0xffff80,
b'\xaa' * (len(test_data) + 256))
rq_pause_toggle.next = pause
rc_pause_toggle.next = pause
read_desc_source.send([(pcie_addr, axi_addr,
len(test_data), cur_tag)])
yield read_desc_status_sink.wait(2000)
rq_pause_toggle.next = 0
rc_pause_toggle.next = 0
status = read_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = axi_ram_inst.read_mem(axi_addr & 0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(
axi_addr - 8,
len(test_data) +
16) == b'\xaa' * 8 + test_data + b'\xaa' * 8
cur_tag = (cur_tag + 1) % 256
yield delay(50)
raise StopSimulation
return instances()
def bench():
# Parameters
S_COUNT = 4
M_COUNT = 4
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH / 8)
S_ID_WIDTH = 8
M_ID_WIDTH = S_ID_WIDTH + math.ceil(math.log(M_COUNT, 2))
AWUSER_ENABLE = 0
AWUSER_WIDTH = 1
WUSER_ENABLE = 0
WUSER_WIDTH = 1
BUSER_ENABLE = 0
BUSER_WIDTH = 1
ARUSER_ENABLE = 0
ARUSER_WIDTH = 1
RUSER_ENABLE = 0
RUSER_WIDTH = 1
S_THREADS = [2] * S_COUNT
S_ACCEPT = [16] * S_COUNT
M_REGIONS = 1
M_BASE_ADDR = [0x00000000, 0x01000000, 0x02000000, 0x03000000]
M_ADDR_WIDTH = [24] * M_COUNT * M_REGIONS
M_CONNECT_READ = [0b1111] * M_COUNT
M_CONNECT_WRITE = [0b1111] * M_COUNT
M_ISSUE = [4] * M_COUNT
M_SECURE = [0] * M_COUNT
S_AW_REG_TYPE = [0] * S_COUNT
S_W_REG_TYPE = [0] * S_COUNT
S_B_REG_TYPE = [1] * S_COUNT
S_AR_REG_TYPE = [0] * S_COUNT
S_R_REG_TYPE = [1] * S_COUNT
M_AW_REG_TYPE = [1] * M_COUNT
M_W_REG_TYPE = [2] * M_COUNT
M_B_REG_TYPE = [0] * M_COUNT
M_AR_REG_TYPE = [1] * M_COUNT
M_R_REG_TYPE = [0] * M_COUNT
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axi_awid_list = [Signal(intbv(0)[S_ID_WIDTH:]) for i in range(S_COUNT)]
s_axi_awaddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axi_awlen_list = [Signal(intbv(0)[8:]) for i in range(S_COUNT)]
s_axi_awsize_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axi_awburst_list = [Signal(intbv(0)[2:]) for i in range(S_COUNT)]
s_axi_awlock_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_awcache_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
s_axi_awprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axi_awqos_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
s_axi_awuser_list = [
Signal(intbv(0)[AWUSER_WIDTH:]) for i in range(S_COUNT)
]
s_axi_awvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_wdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axi_wstrb_list = [Signal(intbv(0)[STRB_WIDTH:]) for i in range(S_COUNT)]
s_axi_wlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_wuser_list = [Signal(intbv(0)[WUSER_WIDTH:]) for i in range(S_COUNT)]
s_axi_wvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_bready_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_arid_list = [Signal(intbv(0)[S_ID_WIDTH:]) for i in range(S_COUNT)]
s_axi_araddr_list = [Signal(intbv(0)[ADDR_WIDTH:]) for i in range(S_COUNT)]
s_axi_arlen_list = [Signal(intbv(0)[8:]) for i in range(S_COUNT)]
s_axi_arsize_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axi_arburst_list = [Signal(intbv(0)[2:]) for i in range(S_COUNT)]
s_axi_arlock_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_arcache_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
s_axi_arprot_list = [Signal(intbv(0)[3:]) for i in range(S_COUNT)]
s_axi_arqos_list = [Signal(intbv(0)[4:]) for i in range(S_COUNT)]
s_axi_aruser_list = [
Signal(intbv(0)[ARUSER_WIDTH:]) for i in range(S_COUNT)
]
s_axi_arvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axi_rready_list = [Signal(bool(0)) for i in range(S_COUNT)]
m_axi_awready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axi_wready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axi_bid_list = [Signal(intbv(0)[M_ID_WIDTH:]) for i in range(M_COUNT)]
m_axi_bresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axi_buser_list = [Signal(intbv(0)[BUSER_WIDTH:]) for i in range(M_COUNT)]
m_axi_bvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axi_arready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axi_rid_list = [Signal(intbv(0)[M_ID_WIDTH:]) for i in range(M_COUNT)]
m_axi_rdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(M_COUNT)]
m_axi_rresp_list = [Signal(intbv(0)[2:]) for i in range(M_COUNT)]
m_axi_rlast_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axi_ruser_list = [Signal(intbv(0)[RUSER_WIDTH:]) for i in range(M_COUNT)]
m_axi_rvalid_list = [Signal(bool(0)) for i in range(M_COUNT)]
s_axi_awid = ConcatSignal(*reversed(s_axi_awid_list))
s_axi_awaddr = ConcatSignal(*reversed(s_axi_awaddr_list))
s_axi_awlen = ConcatSignal(*reversed(s_axi_awlen_list))
s_axi_awsize = ConcatSignal(*reversed(s_axi_awsize_list))
s_axi_awburst = ConcatSignal(*reversed(s_axi_awburst_list))
s_axi_awlock = ConcatSignal(*reversed(s_axi_awlock_list))
s_axi_awcache = ConcatSignal(*reversed(s_axi_awcache_list))
s_axi_awprot = ConcatSignal(*reversed(s_axi_awprot_list))
s_axi_awqos = ConcatSignal(*reversed(s_axi_awqos_list))
s_axi_awuser = ConcatSignal(*reversed(s_axi_awuser_list))
s_axi_awvalid = ConcatSignal(*reversed(s_axi_awvalid_list))
s_axi_wdata = ConcatSignal(*reversed(s_axi_wdata_list))
s_axi_wstrb = ConcatSignal(*reversed(s_axi_wstrb_list))
s_axi_wlast = ConcatSignal(*reversed(s_axi_wlast_list))
s_axi_wuser = ConcatSignal(*reversed(s_axi_wuser_list))
s_axi_wvalid = ConcatSignal(*reversed(s_axi_wvalid_list))
s_axi_bready = ConcatSignal(*reversed(s_axi_bready_list))
s_axi_arid = ConcatSignal(*reversed(s_axi_arid_list))
s_axi_araddr = ConcatSignal(*reversed(s_axi_araddr_list))
s_axi_arlen = ConcatSignal(*reversed(s_axi_arlen_list))
s_axi_arsize = ConcatSignal(*reversed(s_axi_arsize_list))
s_axi_arburst = ConcatSignal(*reversed(s_axi_arburst_list))
s_axi_arlock = ConcatSignal(*reversed(s_axi_arlock_list))
s_axi_arcache = ConcatSignal(*reversed(s_axi_arcache_list))
s_axi_arprot = ConcatSignal(*reversed(s_axi_arprot_list))
s_axi_arqos = ConcatSignal(*reversed(s_axi_arqos_list))
s_axi_aruser = ConcatSignal(*reversed(s_axi_aruser_list))
s_axi_arvalid = ConcatSignal(*reversed(s_axi_arvalid_list))
s_axi_rready = ConcatSignal(*reversed(s_axi_rready_list))
m_axi_awready = ConcatSignal(*reversed(m_axi_awready_list))
m_axi_wready = ConcatSignal(*reversed(m_axi_wready_list))
m_axi_bid = ConcatSignal(*reversed(m_axi_bid_list))
m_axi_bresp = ConcatSignal(*reversed(m_axi_bresp_list))
m_axi_buser = ConcatSignal(*reversed(m_axi_buser_list))
m_axi_bvalid = ConcatSignal(*reversed(m_axi_bvalid_list))
m_axi_arready = ConcatSignal(*reversed(m_axi_arready_list))
m_axi_rid = ConcatSignal(*reversed(m_axi_rid_list))
m_axi_rdata = ConcatSignal(*reversed(m_axi_rdata_list))
m_axi_rresp = ConcatSignal(*reversed(m_axi_rresp_list))
m_axi_rlast = ConcatSignal(*reversed(m_axi_rlast_list))
m_axi_ruser = ConcatSignal(*reversed(m_axi_ruser_list))
m_axi_rvalid = ConcatSignal(*reversed(m_axi_rvalid_list))
# Outputs
s_axi_awready = Signal(intbv(0)[S_COUNT:])
s_axi_wready = Signal(intbv(0)[S_COUNT:])
s_axi_bid = Signal(intbv(0)[S_COUNT * S_ID_WIDTH:])
s_axi_bresp = Signal(intbv(0)[S_COUNT * 2:])
s_axi_buser = Signal(intbv(0)[S_COUNT * BUSER_WIDTH:])
s_axi_bvalid = Signal(intbv(0)[S_COUNT:])
s_axi_arready = Signal(intbv(0)[S_COUNT:])
s_axi_rid = Signal(intbv(0)[S_COUNT * S_ID_WIDTH:])
s_axi_rdata = Signal(intbv(0)[S_COUNT * DATA_WIDTH:])
s_axi_rresp = Signal(intbv(0)[S_COUNT * 2:])
s_axi_rlast = Signal(intbv(0)[S_COUNT:])
s_axi_ruser = Signal(intbv(0)[S_COUNT * RUSER_WIDTH:])
s_axi_rvalid = Signal(intbv(0)[S_COUNT:])
m_axi_awid = Signal(intbv(0)[M_COUNT * M_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[M_COUNT * ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[M_COUNT * 8:])
m_axi_awsize = Signal(intbv(0)[M_COUNT * 3:])
m_axi_awburst = Signal(intbv(0)[M_COUNT * 2:])
m_axi_awlock = Signal(intbv(0)[M_COUNT:])
m_axi_awcache = Signal(intbv(0)[M_COUNT * 4:])
m_axi_awprot = Signal(intbv(0)[M_COUNT * 3:])
m_axi_awqos = Signal(intbv(0)[M_COUNT * 4:])
m_axi_awregion = Signal(intbv(0)[M_COUNT * 4:])
m_axi_awuser = Signal(intbv(0)[M_COUNT * AWUSER_WIDTH:])
m_axi_awvalid = Signal(intbv(0)[M_COUNT:])
m_axi_wdata = Signal(intbv(0)[M_COUNT * DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[M_COUNT * STRB_WIDTH:])
m_axi_wlast = Signal(intbv(0)[M_COUNT:])
m_axi_wuser = Signal(intbv(0)[M_COUNT * WUSER_WIDTH:])
m_axi_wvalid = Signal(intbv(0)[M_COUNT:])
m_axi_bready = Signal(intbv(0)[M_COUNT:])
m_axi_arid = Signal(intbv(0)[M_COUNT * M_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[M_COUNT * ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[M_COUNT * 8:])
m_axi_arsize = Signal(intbv(0)[M_COUNT * 3:])
m_axi_arburst = Signal(intbv(0)[M_COUNT * 2:])
m_axi_arlock = Signal(intbv(0)[M_COUNT:])
m_axi_arcache = Signal(intbv(0)[M_COUNT * 4:])
m_axi_arprot = Signal(intbv(0)[M_COUNT * 3:])
m_axi_arqos = Signal(intbv(0)[M_COUNT * 4:])
m_axi_arregion = Signal(intbv(0)[M_COUNT * 4:])
m_axi_aruser = Signal(intbv(0)[M_COUNT * ARUSER_WIDTH:])
m_axi_arvalid = Signal(intbv(0)[M_COUNT:])
m_axi_rready = Signal(intbv(0)[M_COUNT:])
s_axi_awready_list = [s_axi_awready(i) for i in range(S_COUNT)]
s_axi_wready_list = [s_axi_wready(i) for i in range(S_COUNT)]
s_axi_bid_list = [
s_axi_bid((i + 1) * S_ID_WIDTH, i * S_ID_WIDTH) for i in range(S_COUNT)
]
s_axi_bresp_list = [
s_axi_bresp((i + 1) * 2, i * 2) for i in range(S_COUNT)
]
s_axi_buser_list = [
s_axi_buser((i + 1) * BUSER_WIDTH, i * BUSER_WIDTH)
for i in range(S_COUNT)
]
s_axi_bvalid_list = [s_axi_bvalid(i) for i in range(S_COUNT)]
s_axi_arready_list = [s_axi_arready(i) for i in range(S_COUNT)]
s_axi_rid_list = [
s_axi_rid((i + 1) * S_ID_WIDTH, i * S_ID_WIDTH) for i in range(S_COUNT)
]
s_axi_rdata_list = [
s_axi_rdata((i + 1) * DATA_WIDTH, i * DATA_WIDTH)
for i in range(S_COUNT)
]
s_axi_rresp_list = [
s_axi_rresp((i + 1) * 2, i * 2) for i in range(S_COUNT)
]
s_axi_rlast_list = [s_axi_rlast(i) for i in range(S_COUNT)]
s_axi_ruser_list = [
s_axi_ruser((i + 1) * RUSER_WIDTH, i * RUSER_WIDTH)
for i in range(S_COUNT)
]
s_axi_rvalid_list = [s_axi_rvalid(i) for i in range(S_COUNT)]
m_axi_awid_list = [
m_axi_awid((i + 1) * M_ID_WIDTH, i * M_ID_WIDTH)
for i in range(M_COUNT)
]
m_axi_awaddr_list = [
m_axi_awaddr((i + 1) * ADDR_WIDTH, i * ADDR_WIDTH)
for i in range(M_COUNT)
]
m_axi_awlen_list = [
m_axi_awlen((i + 1) * 8, i * 8) for i in range(M_COUNT)
]
m_axi_awsize_list = [
m_axi_awsize((i + 1) * 3, i * 3) for i in range(M_COUNT)
]
m_axi_awburst_list = [
m_axi_awburst((i + 1) * 2, i * 2) for i in range(M_COUNT)
]
m_axi_awlock_list = [m_axi_awlock(i) for i in range(M_COUNT)]
m_axi_awcache_list = [
m_axi_awcache((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_awprot_list = [
m_axi_awprot((i + 1) * 3, i * 3) for i in range(M_COUNT)
]
m_axi_awqos_list = [
m_axi_awqos((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_awregion_list = [
m_axi_awregion((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_awuser_list = [
m_axi_awuser((i + 1) * AWUSER_WIDTH, i * AWUSER_WIDTH)
for i in range(M_COUNT)
]
m_axi_awvalid_list = [m_axi_awvalid(i) for i in range(M_COUNT)]
m_axi_wdata_list = [
m_axi_wdata((i + 1) * DATA_WIDTH, i * DATA_WIDTH)
for i in range(M_COUNT)
]
m_axi_wstrb_list = [
m_axi_wstrb((i + 1) * STRB_WIDTH, i * STRB_WIDTH)
for i in range(M_COUNT)
]
m_axi_wlast_list = [m_axi_wlast(i) for i in range(M_COUNT)]
m_axi_wuser_list = [
m_axi_wuser((i + 1) * WUSER_WIDTH, i * WUSER_WIDTH)
for i in range(M_COUNT)
]
m_axi_wvalid_list = [m_axi_wvalid(i) for i in range(M_COUNT)]
m_axi_bready_list = [m_axi_bready(i) for i in range(M_COUNT)]
m_axi_arid_list = [
m_axi_arid((i + 1) * M_ID_WIDTH, i * M_ID_WIDTH)
for i in range(M_COUNT)
]
m_axi_araddr_list = [
m_axi_araddr((i + 1) * ADDR_WIDTH, i * ADDR_WIDTH)
for i in range(M_COUNT)
]
m_axi_arlen_list = [
m_axi_arlen((i + 1) * 8, i * 8) for i in range(M_COUNT)
]
m_axi_arsize_list = [
m_axi_arsize((i + 1) * 3, i * 3) for i in range(M_COUNT)
]
m_axi_arburst_list = [
m_axi_arburst((i + 1) * 2, i * 2) for i in range(M_COUNT)
]
m_axi_arlock_list = [m_axi_arlock(i) for i in range(M_COUNT)]
m_axi_arcache_list = [
m_axi_arcache((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_arprot_list = [
m_axi_arprot((i + 1) * 3, i * 3) for i in range(M_COUNT)
]
m_axi_arqos_list = [
m_axi_arqos((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_arregion_list = [
m_axi_arregion((i + 1) * 4, i * 4) for i in range(M_COUNT)
]
m_axi_aruser_list = [
m_axi_aruser((i + 1) * ARUSER_WIDTH, i * ARUSER_WIDTH)
for i in range(M_COUNT)
]
m_axi_arvalid_list = [m_axi_arvalid(i) for i in range(M_COUNT)]
m_axi_rready_list = [m_axi_rready(i) for i in range(M_COUNT)]
# AXI4 masters
axi_master_inst_list = []
axi_master_pause_list = []
axi_master_logic = []
for k in range(S_COUNT):
m = axi.AXIMaster()
p = Signal(bool(False))
axi_master_inst_list.append(m)
axi_master_pause_list.append(p)
axi_master_logic.append(
m.create_logic(clk,
rst,
m_axi_awid=s_axi_awid_list[k],
m_axi_awaddr=s_axi_awaddr_list[k],
m_axi_awlen=s_axi_awlen_list[k],
m_axi_awsize=s_axi_awsize_list[k],
m_axi_awburst=s_axi_awburst_list[k],
m_axi_awlock=s_axi_awlock_list[k],
m_axi_awcache=s_axi_awcache_list[k],
m_axi_awprot=s_axi_awprot_list[k],
m_axi_awqos=s_axi_awqos_list[k],
m_axi_awvalid=s_axi_awvalid_list[k],
m_axi_awready=s_axi_awready_list[k],
m_axi_wdata=s_axi_wdata_list[k],
m_axi_wstrb=s_axi_wstrb_list[k],
m_axi_wlast=s_axi_wlast_list[k],
m_axi_wvalid=s_axi_wvalid_list[k],
m_axi_wready=s_axi_wready_list[k],
m_axi_bid=s_axi_bid_list[k],
m_axi_bresp=s_axi_bresp_list[k],
m_axi_bvalid=s_axi_bvalid_list[k],
m_axi_bready=s_axi_bready_list[k],
m_axi_arid=s_axi_arid_list[k],
m_axi_araddr=s_axi_araddr_list[k],
m_axi_arlen=s_axi_arlen_list[k],
m_axi_arsize=s_axi_arsize_list[k],
m_axi_arburst=s_axi_arburst_list[k],
m_axi_arlock=s_axi_arlock_list[k],
m_axi_arcache=s_axi_arcache_list[k],
m_axi_arprot=s_axi_arprot_list[k],
m_axi_arqos=s_axi_arqos_list[k],
m_axi_arvalid=s_axi_arvalid_list[k],
m_axi_arready=s_axi_arready_list[k],
m_axi_rid=s_axi_rid_list[k],
m_axi_rdata=s_axi_rdata_list[k],
m_axi_rresp=s_axi_rresp_list[k],
m_axi_rlast=s_axi_rlast_list[k],
m_axi_rvalid=s_axi_rvalid_list[k],
m_axi_rready=s_axi_rready_list[k],
pause=p,
name='master_%d' % k))
# AXI4 RAM models
axi_ram_inst_list = []
axi_ram_pause_list = []
axi_ram_logic = []
for k in range(M_COUNT):
r = axi.AXIRam(2**16)
p = Signal(bool(False))
axi_ram_inst_list.append(r)
axi_ram_pause_list.append(p)
axi_ram_logic.append(
r.create_port(clk,
s_axi_awid=m_axi_awid_list[k],
s_axi_awaddr=m_axi_awaddr_list[k],
s_axi_awlen=m_axi_awlen_list[k],
s_axi_awsize=m_axi_awsize_list[k],
s_axi_awburst=m_axi_awburst_list[k],
s_axi_awlock=m_axi_awlock_list[k],
s_axi_awcache=m_axi_awcache_list[k],
s_axi_awprot=m_axi_awprot_list[k],
s_axi_awvalid=m_axi_awvalid_list[k],
s_axi_awready=m_axi_awready_list[k],
s_axi_wdata=m_axi_wdata_list[k],
s_axi_wstrb=m_axi_wstrb_list[k],
s_axi_wlast=m_axi_wlast_list[k],
s_axi_wvalid=m_axi_wvalid_list[k],
s_axi_wready=m_axi_wready_list[k],
s_axi_bid=m_axi_bid_list[k],
s_axi_bresp=m_axi_bresp_list[k],
s_axi_bvalid=m_axi_bvalid_list[k],
s_axi_bready=m_axi_bready_list[k],
s_axi_arid=m_axi_arid_list[k],
s_axi_araddr=m_axi_araddr_list[k],
s_axi_arlen=m_axi_arlen_list[k],
s_axi_arsize=m_axi_arsize_list[k],
s_axi_arburst=m_axi_arburst_list[k],
s_axi_arlock=m_axi_arlock_list[k],
s_axi_arcache=m_axi_arcache_list[k],
s_axi_arprot=m_axi_arprot_list[k],
s_axi_arvalid=m_axi_arvalid_list[k],
s_axi_arready=m_axi_arready_list[k],
s_axi_rid=m_axi_rid_list[k],
s_axi_rdata=m_axi_rdata_list[k],
s_axi_rresp=m_axi_rresp_list[k],
s_axi_rlast=m_axi_rlast_list[k],
s_axi_rvalid=m_axi_rvalid_list[k],
s_axi_rready=m_axi_rready_list[k],
pause=p,
name='ram_%d' % k))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axi_awid=s_axi_awid,
s_axi_awaddr=s_axi_awaddr,
s_axi_awlen=s_axi_awlen,
s_axi_awsize=s_axi_awsize,
s_axi_awburst=s_axi_awburst,
s_axi_awlock=s_axi_awlock,
s_axi_awcache=s_axi_awcache,
s_axi_awprot=s_axi_awprot,
s_axi_awqos=s_axi_awqos,
s_axi_awuser=s_axi_awuser,
s_axi_awvalid=s_axi_awvalid,
s_axi_awready=s_axi_awready,
s_axi_wdata=s_axi_wdata,
s_axi_wstrb=s_axi_wstrb,
s_axi_wlast=s_axi_wlast,
s_axi_wuser=s_axi_wuser,
s_axi_wvalid=s_axi_wvalid,
s_axi_wready=s_axi_wready,
s_axi_bid=s_axi_bid,
s_axi_bresp=s_axi_bresp,
s_axi_buser=s_axi_buser,
s_axi_bvalid=s_axi_bvalid,
s_axi_bready=s_axi_bready,
s_axi_arid=s_axi_arid,
s_axi_araddr=s_axi_araddr,
s_axi_arlen=s_axi_arlen,
s_axi_arsize=s_axi_arsize,
s_axi_arburst=s_axi_arburst,
s_axi_arlock=s_axi_arlock,
s_axi_arcache=s_axi_arcache,
s_axi_arprot=s_axi_arprot,
s_axi_arqos=s_axi_arqos,
s_axi_aruser=s_axi_aruser,
s_axi_arvalid=s_axi_arvalid,
s_axi_arready=s_axi_arready,
s_axi_rid=s_axi_rid,
s_axi_rdata=s_axi_rdata,
s_axi_rresp=s_axi_rresp,
s_axi_rlast=s_axi_rlast,
s_axi_ruser=s_axi_ruser,
s_axi_rvalid=s_axi_rvalid,
s_axi_rready=s_axi_rready,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awqos=m_axi_awqos,
m_axi_awregion=m_axi_awregion,
m_axi_awuser=m_axi_awuser,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wuser=m_axi_wuser,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_buser=m_axi_buser,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arqos=m_axi_arqos,
m_axi_arregion=m_axi_arregion,
m_axi_aruser=m_axi_aruser,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_ruser=m_axi_ruser,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not all([axi_master_inst_list[k].idle()
for k in range(S_COUNT)]):
yield clk.posedge
def wait_pause_master():
while not all([axi_master_inst_list[k].idle()
for k in range(S_COUNT)]):
for k in range(S_COUNT):
axi_master_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
axi_master_pause_list[k].next = False
yield clk.posedge
def wait_pause_slave():
while not all([axi_master_inst_list[k].idle()
for k in range(S_COUNT)]):
for k in range(M_COUNT):
axi_ram_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(M_COUNT):
axi_ram_pause_list[k].next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_master_inst_list[0].init_write(addr, test_data)
yield axi_master_inst_list[0].wait()
yield clk.posedge
data = axi_ram_inst_list[0].read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst_list[0].read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_ram_inst_list[0].write_mem(addr, test_data)
axi_master_inst_list[0].init_read(addr, len(test_data))
yield axi_master_inst_list[0].wait()
yield clk.posedge
data = axi_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: one to many")
current_test.next = 3
addr = 4
test_data = b'\x11\x22\x33\x44'
for k in range(S_COUNT):
axi_master_inst_list[0].init_write(addr + M_BASE_ADDR[k],
test_data)
yield axi_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axi_ram_inst_list[k].read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
for k in range(S_COUNT):
assert axi_ram_inst_list[k].read_mem(addr,
len(test_data)) == test_data
for k in range(S_COUNT):
axi_master_inst_list[0].init_read(addr + M_BASE_ADDR[k],
len(test_data))
yield axi_master_inst_list[0].wait()
yield clk.posedge
for k in range(S_COUNT):
data = axi_master_inst_list[0].get_read_data()
assert data[0] == addr + M_BASE_ADDR[k]
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 4: many to one")
current_test.next = 4
for k in range(M_COUNT):
axi_master_inst_list[k].init_write(k * 4,
bytearray([(k + 1) * 17] * 4))
for k in range(M_COUNT):
yield axi_master_inst_list[k].wait()
yield clk.posedge
data = axi_ram_inst_list[0].read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
for k in range(M_COUNT):
assert axi_ram_inst_list[0].read_mem(k * 4, 4) == bytearray(
[(k + 1) * 17] * 4)
for k in range(M_COUNT):
axi_master_inst_list[k].init_read(k * 4, 4)
for k in range(M_COUNT):
yield axi_master_inst_list[k].wait()
yield clk.posedge
for k in range(M_COUNT):
data = axi_master_inst_list[k].get_read_data()
assert data[0] == k * 4
assert data[1] == bytearray([(k + 1) * 17] * 4)
yield delay(100)
yield clk.posedge
print("test 10: transaction limit and ordering test")
current_test.next = 10
length = 256
test_data = bytearray([x % 256 for x in range(length)])
for k in range(10):
axi_master_inst_list[0].init_write(length * k + M_BASE_ADDR[0],
bytearray([k + 1] * length))
yield axi_master_inst_list[0].wait()
yield clk.posedge
for k in range(10):
data = axi_ram_inst_list[0].read_mem((length * k) & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
for k in range(10):
assert axi_ram_inst_list[0].read_mem(
length * k, length) == bytearray([k + 1] * length)
for k in range(10):
axi_master_inst_list[0].init_read(length * k + M_BASE_ADDR[0],
length)
yield axi_master_inst_list[0].wait()
yield clk.posedge
for k in range(10):
data = axi_master_inst_list[0].get_read_data()
assert data[0] == length * k + M_BASE_ADDR[0]
assert data[1] == bytearray([k + 1] * length)
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
#addr = 256*(16*offset+length)+offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst_list[0].write_mem(addr & 0xffffff80,
b'\xAA' * (length + 256))
axi_master_inst_list[0].init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axi_ram_inst_list[0].read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst_list[0].read_mem(addr,
length) == test_data
assert axi_ram_inst_list[0].read_mem(addr - 1,
1) == b'\xAA'
assert axi_ram_inst_list[0].read_mem(addr + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
#addr = 256*(16*offset+length)+offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst_list[0].write_mem(addr, test_data)
axi_master_inst_list[0].init_read(addr, length)
yield wait()
yield clk.posedge
data = axi_master_inst_list[0].get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 7: concurrent operations")
current_test.next = 7
for count in [1, 2, 4, 8]:
for stride in [2, 3, 5, 7]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("count %d, stride %d" % (count, stride))
for k in range(S_COUNT):
for l in range(count):
ram = ((k * 61 + l) * stride) % M_COUNT
offset = k * 256 + l * 4
axi_ram_inst_list[ram].write_mem(
offset, b'\xAA' * 4)
axi_master_inst_list[k].init_write(
M_BASE_ADDR[ram] + offset,
bytearray([0xaa, k, l, 0xaa]))
ram = ((k * 61 + l + 67) * stride) % M_COUNT
offset = k * 256 + l * 4
axi_ram_inst_list[ram].write_mem(
offset + 0x8000, bytearray([0xaa, k, l, 0xaa]))
axi_master_inst_list[k].init_read(
M_BASE_ADDR[ram] + offset + 0x8000, 4)
yield wait()
yield clk.posedge
for k in range(S_COUNT):
for l in range(count):
ram = ((k * 61 + l) * stride) % M_COUNT
offset = k * 256 + l * 4
axi_ram_inst_list[ram].read_mem(
offset, 4) == bytearray([0xaa, k, l, 0xaa])
ram = ((k * 61 + l + 67) * stride) % M_COUNT
offset = k * 256 + l * 4
data = axi_master_inst_list[k].get_read_data()
assert data[
0] == M_BASE_ADDR[ram] + offset + 0x8000
assert data[1] == bytearray([0xaa, k, l, 0xaa])
yield delay(100)
yield clk.posedge
print("test 8: bad write")
current_test.next = 8
axi_master_inst_list[0].init_write(0xff000000, b'\xDE\xAD\xBE\xEF')
yield axi_master_inst_list[0].wait()
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 9: bad read")
current_test.next = 9
axi_master_inst_list[0].init_read(0xff000000, 4)
yield axi_master_inst_list[0].wait()
yield clk.posedge
data = axi_master_inst_list[0].get_read_data()
assert data[0] == 0xff000000
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
AXIS_PCIE_CQ_USER_WIDTH = 85
AXIS_PCIE_CC_USER_WIDTH = 33
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
m_axis_cc_tready = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
completer_id = Signal(intbv(0)[16:])
completer_id_enable = Signal(bool(0))
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_cc_tvalid = Signal(bool(0))
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(5)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(3)[4:])
m_axi_awprot = Signal(intbv(2)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(5)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(3)[4:])
m_axi_arprot = Signal(intbv(2)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
# Clock and Reset Interface
user_clk=Signal(bool(0))
user_reset=Signal(bool(0))
sys_clk=Signal(bool(0))
sys_reset=Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(
user_clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
name='port0'
)
# PCIe devices
rc = pcie.RootComplex()
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 250e6
dev.functions[0].configure_bar(0, 16*1024*1024)
rc.make_port().connect(dev)
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_rq_tuser=Signal(intbv(0)[60:]),
s_axis_rq_tlast=Signal(bool(0)),
s_axis_rq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_rq_tvalid=Signal(bool(0)),
s_axis_rq_tready=Signal(bool(1)),
# pcie_rq_seq_num=pcie_rq_seq_num,
# pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_rc_tuser=Signal(intbv(0)[75:]),
m_axis_rc_tlast=Signal(bool(0)),
m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_rc_tvalid=Signal(bool(0)),
m_axis_rc_tready=Signal(bool(0)),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tvalid=s_axis_cq_tvalid,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tvalid=m_axis_cc_tvalid,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
completer_id=completer_id,
completer_id_enable=completer_id_enable,
max_payload_size=max_payload_size,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor
)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
status_error_cor_asserted = Signal(bool(0))
status_error_uncor_asserted = Signal(bool(0))
@always(user_clk.posedge)
def monitor():
if (status_error_cor):
status_error_cor_asserted.next = 1
if (status_error_uncor):
status_error_uncor_asserted.next = 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
max_payload_size.next = 0
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate()
dev_bar0 = rc.tree[0][0].bar[0]
yield delay(100)
yield clk.posedge
print("test 2: memory write")
current_test.next = 2
pcie_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
yield rc.mem_write(dev_bar0+pcie_addr, test_data)
yield delay(300)
data = axi_ram_inst.read_mem(pcie_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
assert axi_ram_inst.read_mem(pcie_addr, len(test_data)) == test_data
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
yield delay(100)
yield clk.posedge
print("test 3: memory read")
current_test.next = 3
pcie_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(pcie_addr, test_data)
data = axi_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
val = yield from rc.mem_read(dev_bar0+pcie_addr, len(test_data), 1000)
print(val)
assert val == test_data
assert not status_error_cor_asserted
assert not status_error_uncor_asserted
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH / 8)
ID_WIDTH = 8
AWUSER_ENABLE = 0
AWUSER_WIDTH = 1
WUSER_ENABLE = 0
WUSER_WIDTH = 1
BUSER_ENABLE = 0
BUSER_WIDTH = 1
ARUSER_ENABLE = 0
ARUSER_WIDTH = 1
RUSER_ENABLE = 0
RUSER_WIDTH = 1
WRITE_FIFO_DEPTH = 32
READ_FIFO_DEPTH = 32
WRITE_FIFO_DELAY = 0
READ_FIFO_DELAY = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axi_awid = Signal(intbv(0)[ID_WIDTH:])
s_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axi_awlen = Signal(intbv(0)[8:])
s_axi_awsize = Signal(intbv(0)[3:])
s_axi_awburst = Signal(intbv(0)[2:])
s_axi_awlock = Signal(bool(0))
s_axi_awcache = Signal(intbv(0)[4:])
s_axi_awprot = Signal(intbv(0)[3:])
s_axi_awqos = Signal(intbv(0)[4:])
s_axi_awregion = Signal(intbv(0)[4:])
s_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
s_axi_awvalid = Signal(bool(0))
s_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
s_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
s_axi_wlast = Signal(bool(0))
s_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
s_axi_wvalid = Signal(bool(0))
s_axi_bready = Signal(bool(0))
s_axi_arid = Signal(intbv(0)[ID_WIDTH:])
s_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
s_axi_arlen = Signal(intbv(0)[8:])
s_axi_arsize = Signal(intbv(0)[3:])
s_axi_arburst = Signal(intbv(0)[2:])
s_axi_arlock = Signal(bool(0))
s_axi_arcache = Signal(intbv(0)[4:])
s_axi_arprot = Signal(intbv(0)[3:])
s_axi_arqos = Signal(intbv(0)[4:])
s_axi_arregion = Signal(intbv(0)[4:])
s_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
s_axi_arvalid = Signal(bool(0))
s_axi_rready = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
m_axi_bvalid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
m_axi_rvalid = Signal(bool(0))
# Outputs
s_axi_awready = Signal(bool(0))
s_axi_wready = Signal(bool(0))
s_axi_bid = Signal(intbv(0)[ID_WIDTH:])
s_axi_bresp = Signal(intbv(0)[2:])
s_axi_buser = Signal(intbv(0)[BUSER_WIDTH:])
s_axi_bvalid = Signal(bool(0))
s_axi_arready = Signal(bool(0))
s_axi_rid = Signal(intbv(0)[ID_WIDTH:])
s_axi_rdata = Signal(intbv(0)[DATA_WIDTH:])
s_axi_rresp = Signal(intbv(0)[2:])
s_axi_rlast = Signal(bool(0))
s_axi_ruser = Signal(intbv(0)[RUSER_WIDTH:])
s_axi_rvalid = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(0)[3:])
m_axi_awburst = Signal(intbv(0)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(0)[4:])
m_axi_awprot = Signal(intbv(0)[3:])
m_axi_awqos = Signal(intbv(0)[4:])
m_axi_awregion = Signal(intbv(0)[4:])
m_axi_awuser = Signal(intbv(0)[AWUSER_WIDTH:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wuser = Signal(intbv(0)[WUSER_WIDTH:])
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(0)[3:])
m_axi_arburst = Signal(intbv(0)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(0)[4:])
m_axi_arprot = Signal(intbv(0)[3:])
m_axi_arqos = Signal(intbv(0)[4:])
m_axi_arregion = Signal(intbv(0)[4:])
m_axi_aruser = Signal(intbv(0)[ARUSER_WIDTH:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
# AXI4 master
axi_master_inst = axi.AXIMaster()
axi_master_pause = Signal(bool(False))
axi_master_logic = axi_master_inst.create_logic(
clk,
rst,
m_axi_awid=s_axi_awid,
m_axi_awaddr=s_axi_awaddr,
m_axi_awlen=s_axi_awlen,
m_axi_awsize=s_axi_awsize,
m_axi_awburst=s_axi_awburst,
m_axi_awlock=s_axi_awlock,
m_axi_awcache=s_axi_awcache,
m_axi_awprot=s_axi_awprot,
m_axi_awqos=s_axi_awqos,
m_axi_awregion=s_axi_awregion,
m_axi_awvalid=s_axi_awvalid,
m_axi_awready=s_axi_awready,
m_axi_wdata=s_axi_wdata,
m_axi_wstrb=s_axi_wstrb,
m_axi_wlast=s_axi_wlast,
m_axi_wvalid=s_axi_wvalid,
m_axi_wready=s_axi_wready,
m_axi_bid=s_axi_bid,
m_axi_bresp=s_axi_bresp,
m_axi_bvalid=s_axi_bvalid,
m_axi_bready=s_axi_bready,
m_axi_arid=s_axi_arid,
m_axi_araddr=s_axi_araddr,
m_axi_arlen=s_axi_arlen,
m_axi_arsize=s_axi_arsize,
m_axi_arburst=s_axi_arburst,
m_axi_arlock=s_axi_arlock,
m_axi_arcache=s_axi_arcache,
m_axi_arprot=s_axi_arprot,
m_axi_arqos=s_axi_arqos,
m_axi_arregion=s_axi_arregion,
m_axi_arvalid=s_axi_arvalid,
m_axi_arready=s_axi_arready,
m_axi_rid=s_axi_rid,
m_axi_rdata=s_axi_rdata,
m_axi_rresp=s_axi_rresp,
m_axi_rlast=s_axi_rlast,
m_axi_rvalid=s_axi_rvalid,
m_axi_rready=s_axi_rready,
pause=axi_master_pause,
name='master')
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_pause = Signal(bool(False))
axi_ram_port0 = axi_ram_inst.create_port(clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
pause=axi_ram_pause,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axi_awid=s_axi_awid,
s_axi_awaddr=s_axi_awaddr,
s_axi_awlen=s_axi_awlen,
s_axi_awsize=s_axi_awsize,
s_axi_awburst=s_axi_awburst,
s_axi_awlock=s_axi_awlock,
s_axi_awcache=s_axi_awcache,
s_axi_awprot=s_axi_awprot,
s_axi_awqos=s_axi_awqos,
s_axi_awregion=s_axi_awregion,
s_axi_awuser=s_axi_awuser,
s_axi_awvalid=s_axi_awvalid,
s_axi_awready=s_axi_awready,
s_axi_wdata=s_axi_wdata,
s_axi_wstrb=s_axi_wstrb,
s_axi_wlast=s_axi_wlast,
s_axi_wuser=s_axi_wuser,
s_axi_wvalid=s_axi_wvalid,
s_axi_wready=s_axi_wready,
s_axi_bid=s_axi_bid,
s_axi_bresp=s_axi_bresp,
s_axi_buser=s_axi_buser,
s_axi_bvalid=s_axi_bvalid,
s_axi_bready=s_axi_bready,
s_axi_arid=s_axi_arid,
s_axi_araddr=s_axi_araddr,
s_axi_arlen=s_axi_arlen,
s_axi_arsize=s_axi_arsize,
s_axi_arburst=s_axi_arburst,
s_axi_arlock=s_axi_arlock,
s_axi_arcache=s_axi_arcache,
s_axi_arprot=s_axi_arprot,
s_axi_arqos=s_axi_arqos,
s_axi_arregion=s_axi_arregion,
s_axi_aruser=s_axi_aruser,
s_axi_arvalid=s_axi_arvalid,
s_axi_arready=s_axi_arready,
s_axi_rid=s_axi_rid,
s_axi_rdata=s_axi_rdata,
s_axi_rresp=s_axi_rresp,
s_axi_rlast=s_axi_rlast,
s_axi_ruser=s_axi_ruser,
s_axi_rvalid=s_axi_rvalid,
s_axi_rready=s_axi_rready,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awqos=m_axi_awqos,
m_axi_awregion=m_axi_awregion,
m_axi_awuser=m_axi_awuser,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wuser=m_axi_wuser,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_buser=m_axi_buser,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arqos=m_axi_arqos,
m_axi_arregion=m_axi_arregion,
m_axi_aruser=m_axi_aruser,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_ruser=m_axi_ruser,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not axi_master_inst.idle():
yield clk.posedge
def wait_pause_master():
while not axi_master_inst.idle():
axi_master_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_master_pause.next = False
yield clk.posedge
def wait_pause_slave():
while not axi_master_inst.idle():
axi_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_ram_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_master_inst.init_write(addr, test_data)
yield axi_master_inst.wait()
yield clk.posedge
data = axi_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(addr, test_data)
axi_master_inst.init_read(addr, len(test_data))
yield axi_master_inst.wait()
yield clk.posedge
data = axi_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
#addr = 256*(16*offset+length)+offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(addr & 0xffffff80,
b'\xAA' * (length + 256))
axi_master_inst.init_write(addr, test_data)
yield wait()
yield clk.posedge
data = axi_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr, length) == test_data
assert axi_ram_inst.read_mem(addr - 1, 1) == b'\xAA'
assert axi_ram_inst.read_mem(addr + length, 1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d" % (length, offset))
#addr = 256*(16*offset+length)+offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(addr, test_data)
axi_master_inst.init_read(addr, length)
yield wait()
yield clk.posedge
data = axi_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60
RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6
RQ_SEQ_NUM_ENABLE = 1
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT - 1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
READ_OP_TABLE_SIZE = PCIE_TAG_COUNT
READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH - 1)
WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH - 1)
WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH - 1)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
m_axis_rq_tready = Signal(bool(0))
s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_0 = Signal(bool(0))
s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_1 = Signal(bool(0))
s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_write_desc_valid = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
read_enable = Signal(bool(0))
write_enable = Signal(bool(0))
ext_tag_enable = Signal(bool(0))
requester_id = Signal(intbv(0)[16:])
requester_id_enable = Signal(bool(0))
max_read_request_size = Signal(intbv(0)[3:])
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rc_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
s_axis_write_desc_ready = Signal(bool(0))
m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_write_desc_status_valid = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(5)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(3)[4:])
m_axi_awprot = Signal(intbv(2)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(5)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(3)[4:])
m_axi_arprot = Signal(intbv(2)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(user_clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
name='port0')
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_logic = read_desc_source.create_logic(
user_clk,
user_reset,
tdata=(s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr,
s_axis_read_desc_len, s_axis_read_desc_tag),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
name='read_desc_source')
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
user_clk,
user_reset,
tdata=(m_axis_read_desc_status_tag, ),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink')
write_desc_source = axis_ep.AXIStreamSource()
write_desc_source_logic = write_desc_source.create_logic(
user_clk,
user_reset,
tdata=(s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr,
s_axis_write_desc_len, s_axis_write_desc_tag),
tvalid=s_axis_write_desc_valid,
tready=s_axis_write_desc_ready,
name='write_desc_source')
write_desc_status_sink = axis_ep.AXIStreamSink()
write_desc_status_sink_logic = write_desc_status_sink.create_logic(
user_clk,
user_reset,
tdata=(m_axis_write_desc_status_tag, ),
tvalid=m_axis_write_desc_status_valid,
name='write_desc_status_sink')
# PCIe devices
rc = pcie.RootComplex()
mem_base, mem_data = rc.alloc_region(16 * 1024 * 1024)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
rc.make_port().connect(dev)
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_cq_tuser=Signal(intbv(0)[85:]),
m_axis_cq_tlast=Signal(bool(0)),
m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_cq_tvalid=Signal(bool(0)),
m_axis_cq_tready=Signal(bool(1)),
pcie_cq_np_req=Signal(bool(1)),
pcie_cq_np_req_count=Signal(intbv(0)[6:]),
# Completer Completion Interface
s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_cc_tuser=Signal(intbv(0)[33:]),
s_axis_cc_tlast=Signal(bool(0)),
s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_cc_tvalid=Signal(bool(0)),
s_axis_cc_tready=Signal(bool(0)),
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
pcie_rq_seq_num=s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld=s_axis_rq_seq_num_valid_0,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr,
s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr,
s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr,
s_axis_write_desc_len=s_axis_write_desc_len,
s_axis_write_desc_tag=s_axis_write_desc_tag,
s_axis_write_desc_valid=s_axis_write_desc_valid,
s_axis_write_desc_ready=s_axis_write_desc_ready,
m_axis_write_desc_status_tag=m_axis_write_desc_status_tag,
m_axis_write_desc_status_valid=m_axis_write_desc_status_valid,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
read_enable=read_enable,
write_enable=write_enable,
ext_tag_enable=ext_tag_enable,
requester_id=requester_id,
requester_id_enable=requester_id_enable,
max_read_request_size=max_read_request_size,
max_payload_size=max_payload_size,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
max_payload_size.next = 0
max_read_request_size.next = 2
read_enable.next = 1
write_enable.next = 1
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True)
yield delay(100)
yield user_clk.posedge
print("test 2: PCIe write")
current_test.next = 2
pcie_addr = 0x00000000
axi_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(axi_addr, test_data)
mem_data[pcie_addr:pcie_addr +
len(test_data)] = b'\x00' * len(test_data)
data = axi_ram_inst.read_mem(axi_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
write_desc_source.send([(mem_base + pcie_addr, axi_addr,
len(test_data), cur_tag)])
yield write_desc_status_sink.wait(1000)
yield delay(50)
status = write_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = mem_data[pcie_addr:pcie_addr + 32]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert mem_data[pcie_addr:pcie_addr + len(test_data)] == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield user_clk.posedge
print("test 3: PCIe read")
current_test.next = 3
pcie_addr = 0x00000000
axi_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(axi_addr, b'\x00' * len(test_data))
mem_data[pcie_addr:pcie_addr + len(test_data)] = test_data
data = mem_data[pcie_addr:pcie_addr + 32]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(pcie_addr, axi_addr, len(test_data), cur_tag)])
yield read_desc_status_sink.wait(2000)
status = read_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = axi_ram_inst.read_mem(axi_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(axi_addr, len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXI_DATA_WIDTH = 32
AXI_ADDR_WIDTH = 16
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 16
AXIS_DATA_WIDTH = AXI_DATA_WIDTH
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH > 8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
AXIS_ID_ENABLE = 1
AXIS_ID_WIDTH = 8
AXIS_DEST_ENABLE = 0
AXIS_DEST_WIDTH = 8
AXIS_USER_ENABLE = 1
AXIS_USER_WIDTH = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
ENABLE_SG = 0
ENABLE_UNALIGNED = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_read_desc_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_id = Signal(intbv(0)[AXIS_ID_WIDTH:])
s_axis_read_desc_dest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
s_axis_read_desc_user = Signal(intbv(0)[AXIS_USER_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
m_axis_read_data_tready = Signal(bool(0))
s_axis_write_desc_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_write_desc_valid = Signal(bool(0))
s_axis_write_data_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
s_axis_write_data_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
s_axis_write_data_tvalid = Signal(bool(0))
s_axis_write_data_tlast = Signal(bool(0))
s_axis_write_data_tid = Signal(intbv(0)[AXIS_ID_WIDTH:])
s_axis_write_data_tdest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
s_axis_write_data_tuser = Signal(intbv(0)[AXIS_USER_WIDTH:])
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
read_enable = Signal(bool(0))
write_enable = Signal(bool(0))
write_abort = Signal(bool(0))
# Outputs
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
m_axis_read_data_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
m_axis_read_data_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
m_axis_read_data_tvalid = Signal(bool(0))
m_axis_read_data_tlast = Signal(bool(0))
m_axis_read_data_tid = Signal(intbv(0)[AXIS_ID_WIDTH:])
m_axis_read_data_tdest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
m_axis_read_data_tuser = Signal(intbv(0)[AXIS_USER_WIDTH:])
s_axis_write_desc_ready = Signal(bool(0))
m_axis_write_desc_status_len = Signal(intbv(0)[LEN_WIDTH:])
m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_write_desc_status_id = Signal(intbv(0)[AXIS_ID_WIDTH:])
m_axis_write_desc_status_dest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
m_axis_write_desc_status_user = Signal(intbv(0)[AXIS_USER_WIDTH:])
m_axis_write_desc_status_valid = Signal(bool(0))
s_axis_write_data_tready = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(2)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(0)[4:])
m_axi_awprot = Signal(intbv(0)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(2)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(0)[4:])
m_axi_arprot = Signal(intbv(0)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_pause = Signal(bool(False))
axi_ram_port0 = axi_ram_inst.create_port(clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
pause=axi_ram_pause,
name='port0')
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_pause = Signal(bool(False))
read_desc_source_logic = read_desc_source.create_logic(
clk,
rst,
tdata=(s_axis_read_desc_addr, s_axis_read_desc_len,
s_axis_read_desc_tag, s_axis_read_desc_id,
s_axis_read_desc_dest, s_axis_read_desc_user),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
pause=read_desc_source_pause,
name='read_desc_source')
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
clk,
rst,
tdata=(m_axis_read_desc_status_tag, ),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink')
read_data_sink = axis_ep.AXIStreamSink()
read_data_sink_pause = Signal(bool(False))
read_data_sink_logic = read_data_sink.create_logic(
clk,
rst,
tdata=m_axis_read_data_tdata,
tkeep=m_axis_read_data_tkeep,
tvalid=m_axis_read_data_tvalid,
tready=m_axis_read_data_tready,
tlast=m_axis_read_data_tlast,
tid=m_axis_read_data_tid,
tdest=m_axis_read_data_tdest,
tuser=m_axis_read_data_tuser,
pause=read_data_sink_pause,
name='read_data_sink')
write_desc_source = axis_ep.AXIStreamSource()
write_desc_source_pause = Signal(bool(False))
write_desc_source_logic = write_desc_source.create_logic(
clk,
rst,
tdata=(s_axis_write_desc_addr, s_axis_write_desc_len,
s_axis_write_desc_tag),
tvalid=s_axis_write_desc_valid,
tready=s_axis_write_desc_ready,
pause=write_desc_source_pause,
name='write_desc_source')
write_desc_status_sink = axis_ep.AXIStreamSink()
write_desc_status_sink_logic = write_desc_status_sink.create_logic(
clk,
rst,
tdata=(m_axis_write_desc_status_len, m_axis_write_desc_status_tag,
m_axis_write_desc_status_id, m_axis_write_desc_status_dest,
m_axis_write_desc_status_user),
tvalid=m_axis_write_desc_status_valid,
name='write_desc_status_sink')
write_data_source = axis_ep.AXIStreamSource()
write_data_source_pause = Signal(bool(False))
write_data_source_logic = write_data_source.create_logic(
clk,
rst,
tdata=s_axis_write_data_tdata,
tkeep=s_axis_write_data_tkeep,
tvalid=s_axis_write_data_tvalid,
tready=s_axis_write_data_tready,
tlast=s_axis_write_data_tlast,
tid=s_axis_write_data_tid,
tdest=s_axis_write_data_tdest,
tuser=s_axis_write_data_tuser,
pause=write_data_source_pause,
name='write_data_source')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_read_desc_addr=s_axis_read_desc_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_id=s_axis_read_desc_id,
s_axis_read_desc_dest=s_axis_read_desc_dest,
s_axis_read_desc_user=s_axis_read_desc_user,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
m_axis_read_data_tdata=m_axis_read_data_tdata,
m_axis_read_data_tkeep=m_axis_read_data_tkeep,
m_axis_read_data_tvalid=m_axis_read_data_tvalid,
m_axis_read_data_tready=m_axis_read_data_tready,
m_axis_read_data_tlast=m_axis_read_data_tlast,
m_axis_read_data_tid=m_axis_read_data_tid,
m_axis_read_data_tdest=m_axis_read_data_tdest,
m_axis_read_data_tuser=m_axis_read_data_tuser,
s_axis_write_desc_addr=s_axis_write_desc_addr,
s_axis_write_desc_len=s_axis_write_desc_len,
s_axis_write_desc_tag=s_axis_write_desc_tag,
s_axis_write_desc_valid=s_axis_write_desc_valid,
s_axis_write_desc_ready=s_axis_write_desc_ready,
m_axis_write_desc_status_len=m_axis_write_desc_status_len,
m_axis_write_desc_status_tag=m_axis_write_desc_status_tag,
m_axis_write_desc_status_id=m_axis_write_desc_status_id,
m_axis_write_desc_status_dest=m_axis_write_desc_status_dest,
m_axis_write_desc_status_user=m_axis_write_desc_status_user,
m_axis_write_desc_status_valid=m_axis_write_desc_status_valid,
s_axis_write_data_tdata=s_axis_write_data_tdata,
s_axis_write_data_tkeep=s_axis_write_data_tkeep,
s_axis_write_data_tvalid=s_axis_write_data_tvalid,
s_axis_write_data_tready=s_axis_write_data_tready,
s_axis_write_data_tlast=s_axis_write_data_tlast,
s_axis_write_data_tid=s_axis_write_data_tid,
s_axis_write_data_tdest=s_axis_write_data_tdest,
s_axis_write_data_tuser=s_axis_write_data_tuser,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
read_enable=read_enable,
write_enable=write_enable,
write_abort=write_abort)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while (read_desc_status_sink.empty()
or read_data_sink.empty()) and write_desc_status_sink.empty():
yield clk.posedge
def wait_pause_ram():
while (read_desc_status_sink.empty()
or read_data_sink.empty()) and write_desc_status_sink.empty():
axi_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_ram_pause.next = False
yield clk.posedge
def wait_pause_source():
while (read_desc_status_sink.empty()
or read_data_sink.empty()) and write_desc_status_sink.empty():
write_data_source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
write_data_source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while (read_desc_status_sink.empty()
or read_data_sink.empty()) and write_desc_status_sink.empty():
read_data_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
read_data_sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
read_enable.next = 1
write_enable.next = 1
yield clk.posedge
print("test 1: read")
current_test.next = 1
addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(addr, test_data)
data = axi_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(addr, len(test_data), cur_tag, cur_tag, 0, 0)])
yield read_desc_status_sink.wait(1000)
yield read_data_sink.wait(1000)
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 2: write")
current_test.next = 2
addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
write_desc_source.send([(addr, len(test_data), cur_tag)])
write_data_source.send(axis_ep.AXIStreamFrame(test_data, id=cur_tag))
yield write_desc_status_sink.wait(2000)
status = write_desc_status_sink.recv()
print(status)
data = axi_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 3: various reads")
current_test.next = 3
for length in list(range(1, 33)) + [128]:
for offset in [0, 16, 4096 - 16]:
for wait in wait_normal, wait_pause_ram, wait_pause_source:
print("length %d, offset %d" % (length, offset))
#addr = length * 0x100000000 + offset * 0x10000 + offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(addr, test_data)
data = axi_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(addr, len(test_data), cur_tag,
cur_tag, 0, 0)])
yield wait()
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 4: various writes")
current_test.next = 4
for length in list(range(1, 33)) + [128]:
for offset in [0, 16, 4096 - 16]:
for wait in wait_normal, wait_pause_ram, wait_pause_sink:
print("length %d, offset %d" % (length, offset))
#addr = length * 0x100000000 + offset * 0x10000 + offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
write_desc_source.send([(addr, len(test_data), cur_tag)])
write_data_source.send(
axis_ep.AXIStreamFrame(test_data, id=cur_tag))
yield wait()
status = write_desc_status_sink.recv()
print(status)
data = axi_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr,
len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_axi_awid = Signal(intbv(0)[8:])
port0_axi_awaddr = Signal(intbv(0)[32:])
port0_axi_awlen = Signal(intbv(0)[8:])
port0_axi_awsize = Signal(intbv(0)[3:])
port0_axi_awburst = Signal(intbv(0)[2:])
port0_axi_awlock = Signal(intbv(0)[1:])
port0_axi_awcache = Signal(intbv(0)[4:])
port0_axi_awprot = Signal(intbv(0)[3:])
port0_axi_awqos = Signal(intbv(0)[4:])
port0_axi_awregion = Signal(intbv(0)[4:])
port0_axi_awvalid = Signal(bool(False))
port0_axi_wdata = Signal(intbv(0)[32:])
port0_axi_wstrb = Signal(intbv(0)[4:])
port0_axi_wlast = Signal(bool(False))
port0_axi_wvalid = Signal(bool(False))
port0_axi_bready = Signal(bool(False))
port0_axi_arid = Signal(intbv(0)[8:])
port0_axi_araddr = Signal(intbv(0)[32:])
port0_axi_arlen = Signal(intbv(0)[8:])
port0_axi_arsize = Signal(intbv(0)[3:])
port0_axi_arburst = Signal(intbv(0)[2:])
port0_axi_arlock = Signal(intbv(0)[1:])
port0_axi_arcache = Signal(intbv(0)[4:])
port0_axi_arprot = Signal(intbv(0)[3:])
port0_axi_arqos = Signal(intbv(0)[4:])
port0_axi_arregion = Signal(intbv(0)[4:])
port0_axi_arvalid = Signal(bool(False))
port0_axi_rready = Signal(bool(False))
# Outputs
port0_axi_awready = Signal(bool(False))
port0_axi_wready = Signal(bool(False))
port0_axi_bid = Signal(intbv(0)[8:])
port0_axi_bresp = Signal(intbv(0)[2:])
port0_axi_bvalid = Signal(bool(False))
port0_axi_arready = Signal(bool(False))
port0_axi_rid = Signal(intbv(0)[8:])
port0_axi_rdata = Signal(intbv(0)[32:])
port0_axi_rresp = Signal(intbv(0)[2:])
port0_axi_rlast = Signal(bool(False))
port0_axi_rvalid = Signal(bool(False))
# AXI4 master
axi_master_inst = axi.AXIMaster()
axi_master_pause = Signal(bool(False))
axi_master_logic = axi_master_inst.create_logic(
clk,
rst,
m_axi_awid=port0_axi_awid,
m_axi_awaddr=port0_axi_awaddr,
m_axi_awlen=port0_axi_awlen,
m_axi_awsize=port0_axi_awsize,
m_axi_awburst=port0_axi_awburst,
m_axi_awlock=port0_axi_awlock,
m_axi_awcache=port0_axi_awcache,
m_axi_awprot=port0_axi_awprot,
m_axi_awqos=port0_axi_awqos,
m_axi_awregion=port0_axi_awregion,
m_axi_awvalid=port0_axi_awvalid,
m_axi_awready=port0_axi_awready,
m_axi_wdata=port0_axi_wdata,
m_axi_wstrb=port0_axi_wstrb,
m_axi_wlast=port0_axi_wlast,
m_axi_wvalid=port0_axi_wvalid,
m_axi_wready=port0_axi_wready,
m_axi_bid=port0_axi_bid,
m_axi_bresp=port0_axi_bresp,
m_axi_bvalid=port0_axi_bvalid,
m_axi_bready=port0_axi_bready,
m_axi_arid=port0_axi_arid,
m_axi_araddr=port0_axi_araddr,
m_axi_arlen=port0_axi_arlen,
m_axi_arsize=port0_axi_arsize,
m_axi_arburst=port0_axi_arburst,
m_axi_arlock=port0_axi_arlock,
m_axi_arcache=port0_axi_arcache,
m_axi_arprot=port0_axi_arprot,
m_axi_arqos=port0_axi_arqos,
m_axi_arregion=port0_axi_arregion,
m_axi_arvalid=port0_axi_arvalid,
m_axi_arready=port0_axi_arready,
m_axi_rid=port0_axi_rid,
m_axi_rdata=port0_axi_rdata,
m_axi_rresp=port0_axi_rresp,
m_axi_rlast=port0_axi_rlast,
m_axi_rvalid=port0_axi_rvalid,
m_axi_rready=port0_axi_rready,
pause=axi_master_pause,
name='master')
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_pause = Signal(bool(False))
axi_ram_port0 = axi_ram_inst.create_port(clk,
s_axi_awid=port0_axi_awid,
s_axi_awaddr=port0_axi_awaddr,
s_axi_awlen=port0_axi_awlen,
s_axi_awsize=port0_axi_awsize,
s_axi_awburst=port0_axi_awburst,
s_axi_awlock=port0_axi_awlock,
s_axi_awcache=port0_axi_awcache,
s_axi_awprot=port0_axi_awprot,
s_axi_awvalid=port0_axi_awvalid,
s_axi_awready=port0_axi_awready,
s_axi_wdata=port0_axi_wdata,
s_axi_wstrb=port0_axi_wstrb,
s_axi_wlast=port0_axi_wlast,
s_axi_wvalid=port0_axi_wvalid,
s_axi_wready=port0_axi_wready,
s_axi_bid=port0_axi_bid,
s_axi_bresp=port0_axi_bresp,
s_axi_bvalid=port0_axi_bvalid,
s_axi_bready=port0_axi_bready,
s_axi_arid=port0_axi_arid,
s_axi_araddr=port0_axi_araddr,
s_axi_arlen=port0_axi_arlen,
s_axi_arsize=port0_axi_arsize,
s_axi_arburst=port0_axi_arburst,
s_axi_arlock=port0_axi_arlock,
s_axi_arcache=port0_axi_arcache,
s_axi_arprot=port0_axi_arprot,
s_axi_arvalid=port0_axi_arvalid,
s_axi_arready=port0_axi_arready,
s_axi_rid=port0_axi_rid,
s_axi_rdata=port0_axi_rdata,
s_axi_rresp=port0_axi_rresp,
s_axi_rlast=port0_axi_rlast,
s_axi_rvalid=port0_axi_rvalid,
s_axi_rready=port0_axi_rready,
pause=axi_ram_pause,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while not axi_master_inst.idle():
yield clk.posedge
def wait_pause_master():
while not axi_master_inst.idle():
axi_master_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_master_pause.next = False
yield clk.posedge
def wait_pause_slave():
while not axi_master_inst.idle():
axi_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_ram_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = axi_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
axi_ram_inst.write_mem(0, b'test')
data = axi_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(0, 4) == b'test'
yield delay(100)
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_master_inst.init_write(addr, test_data)
yield axi_master_inst.wait()
yield clk.posedge
data = axi_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr, len(test_data)) == test_data
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
addr = 4
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(addr, test_data)
axi_master_inst.init_read(addr, len(test_data))
yield axi_master_inst.wait()
yield clk.posedge
data = axi_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for size in (2, 1, 0):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d, size %d" %
(length, offset, size))
addr = 256 * (16 * offset + length) + offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(addr & 0xffffff80,
b'\xAA' * (length + 256))
axi_master_inst.init_write(addr, test_data, size=size)
yield wait()
yield clk.posedge
data = axi_ram_inst.read_mem(addr & 0xffffff80, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(addr, length) == test_data
assert axi_ram_inst.read_mem(addr - 1, 1) == b'\xAA'
assert axi_ram_inst.read_mem(addr + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in list(range(1, 8)) + [1024]:
for offset in list(range(4, 8)) + [4096 - 4]:
for size in (2, 1, 0):
for wait in wait_normal, wait_pause_master, wait_pause_slave:
print("length %d, offset %d, size %d" %
(length, offset, size))
addr = 256 * (16 * offset + length) + offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(addr, test_data)
axi_master_inst.init_read(addr, length, size=size)
yield wait()
yield clk.posedge
data = axi_master_inst.get_read_data()
assert data[0] == addr
assert data[1] == test_data
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 128
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RQ_USER_WIDTH = 60
RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6
RQ_SEQ_NUM_ENABLE = 1
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
LEN_WIDTH = 20
TAG_WIDTH = 8
OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH - 1)
TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH - 1)
TX_FC_ENABLE = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rq_tvalid = Signal(bool(0))
s_axis_rq_tlast = Signal(bool(0))
s_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
m_axis_rq_tready = Signal(bool(0))
s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_0 = Signal(bool(0))
s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_1 = Signal(bool(0))
pcie_tx_fc_ph_av = Signal(intbv(0)[8:])
pcie_tx_fc_pd_av = Signal(intbv(0)[12:])
s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_write_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_write_desc_valid = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
enable = Signal(bool(0))
requester_id = Signal(intbv(0)[16:])
requester_id_enable = Signal(bool(0))
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rq_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
m_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
m_axis_rq_seq_num_valid_0 = Signal(bool(0))
m_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
m_axis_rq_seq_num_valid_1 = Signal(bool(0))
s_axis_write_desc_ready = Signal(bool(0))
m_axis_write_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_write_desc_status_valid = Signal(bool(0))
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(4)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(3)[4:])
m_axi_arprot = Signal(intbv(2)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(user_clk,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
name='port0')
write_desc_source = axis_ep.AXIStreamSource()
write_desc_source_logic = write_desc_source.create_logic(
user_clk,
user_reset,
tdata=(s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr,
s_axis_write_desc_len, s_axis_write_desc_tag),
tvalid=s_axis_write_desc_valid,
tready=s_axis_write_desc_ready,
name='write_desc_source')
write_desc_status_sink = axis_ep.AXIStreamSink()
write_desc_status_sink_logic = write_desc_status_sink.create_logic(
user_clk,
user_reset,
tdata=(m_axis_write_desc_status_tag, ),
tvalid=m_axis_write_desc_status_valid,
name='write_desc_status_sink')
# PCIe devices
rc = pcie.RootComplex()
mem_base, mem_data = rc.alloc_region(16 * 1024 * 1024)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 4
dev.user_clock_frequency = 250e6
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_cq_tuser=Signal(intbv(0)[85:]),
m_axis_cq_tlast=Signal(bool(0)),
m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_cq_tvalid=Signal(bool(0)),
m_axis_cq_tready=Signal(bool(1)),
#pcie_cq_np_req=pcie_cq_np_req,
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_cc_tuser=Signal(intbv(0)[33:]),
s_axis_cc_tlast=Signal(bool(0)),
s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_cc_tvalid=Signal(bool(0)),
s_axis_cc_tready=Signal(bool(0)),
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
pcie_rq_seq_num=s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld=s_axis_rq_seq_num_valid_0,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_rc_tuser=Signal(intbv(0)[75:]),
m_axis_rc_tlast=Signal(bool(0)),
m_axis_rc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_rc_tvalid=Signal(bool(0)),
m_axis_rc_tready=Signal(bool(0)),
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Flow Control Interface
cfg_fc_ph=pcie_tx_fc_ph_av,
cfg_fc_pd=pcie_tx_fc_pd_av,
#cfg_fc_nph=cfg_fc_nph,
#cfg_fc_npd=cfg_fc_npd,
#cfg_fc_cplh=cfg_fc_cplh,
#cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=Signal(intbv(0b100)[3:]),
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rq_tdata=s_axis_rq_tdata,
s_axis_rq_tkeep=s_axis_rq_tkeep,
s_axis_rq_tvalid=s_axis_rq_tvalid,
s_axis_rq_tready=s_axis_rq_tready,
s_axis_rq_tlast=s_axis_rq_tlast,
s_axis_rq_tuser=s_axis_rq_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
m_axis_rq_seq_num_0=m_axis_rq_seq_num_0,
m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0,
m_axis_rq_seq_num_1=m_axis_rq_seq_num_1,
m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1,
pcie_tx_fc_ph_av=pcie_tx_fc_ph_av,
pcie_tx_fc_pd_av=pcie_tx_fc_pd_av,
s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr,
s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr,
s_axis_write_desc_len=s_axis_write_desc_len,
s_axis_write_desc_tag=s_axis_write_desc_tag,
s_axis_write_desc_valid=s_axis_write_desc_valid,
s_axis_write_desc_ready=s_axis_write_desc_ready,
m_axis_write_desc_status_tag=m_axis_write_desc_status_tag,
m_axis_write_desc_status_valid=m_axis_write_desc_status_valid,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
enable=enable,
requester_id=requester_id,
requester_id_enable=requester_id_enable,
max_payload_size=max_payload_size)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
cq_pause_toggle = Signal(bool(0))
cc_pause_toggle = Signal(bool(0))
rq_pause_toggle = Signal(bool(0))
rc_pause_toggle = Signal(bool(0))
@instance
def pause_toggle():
while True:
if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle
or rc_pause_toggle):
cq_pause.next = cq_pause_toggle
cc_pause.next = cc_pause_toggle
rq_pause.next = rq_pause_toggle
rc_pause.next = rc_pause_toggle
yield user_clk.posedge
yield user_clk.posedge
yield user_clk.posedge
cq_pause.next = 0
cc_pause.next = 0
rq_pause.next = 0
rc_pause.next = 0
yield user_clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
max_payload_size.next = 0
enable.next = 1
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True)
yield delay(100)
yield user_clk.posedge
print("test 2: PCIe write")
current_test.next = 2
pcie_addr = 0x00000000
axi_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(axi_addr, test_data)
data = axi_ram_inst.read_mem(axi_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
write_desc_source.send([(mem_base + pcie_addr, axi_addr,
len(test_data), cur_tag)])
yield write_desc_status_sink.wait(1000)
yield delay(50)
status = write_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = mem_data[pcie_addr:pcie_addr + 32]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert mem_data[pcie_addr:pcie_addr + len(test_data)] == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield user_clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in list(range(1, 19)) + list(range(128 - 4,
128 + 4)) + [1024]:
for pcie_offset in list(range(8, 13)) + list(
range(4096 - 4, 4096 + 4)):
for axi_offset in list(range(8, 25)) + list(
range(4096 - 16, 4096)):
for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d" %
(length, pcie_offset, axi_offset))
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
pcie_addr = pcie_offset
axi_addr = axi_offset
test_data = bytearray([x % 256 for x in range(length)])
axi_ram_inst.write_mem(
axi_addr & 0xffff80,
b'\x55' * (len(test_data) + 256))
mem_data[(pcie_addr - 1)
& 0xffff80:((pcie_addr - 1) & 0xffff80) +
len(test_data) +
256] = b'\xaa' * (len(test_data) + 256)
axi_ram_inst.write_mem(axi_addr, test_data)
data = axi_ram_inst.read_mem(axi_addr & 0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
rq_pause_toggle.next = pause
write_desc_source.send([
(mem_base + pcie_addr, axi_addr, len(test_data),
cur_tag)
])
yield write_desc_status_sink.wait(4000)
yield delay(50)
rq_pause_toggle.next = 0
status = write_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = mem_data[pcie_addr
& 0xfffff0:(pcie_addr & 0xfffff0) + 64]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert mem_data[pcie_addr - 1:pcie_addr +
len(test_data) +
1] == b'\xaa' + test_data + b'\xaa'
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
