コード例 #1
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
import os, sys, string, random
import veri

NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs

Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 10000  # how many cycles to run before retirment.

import panics
import axiMaster
import axiSlave

ma = axiMaster.axiMasterClass('tb', Monitors, 'mst0_', '', 'MA')
mb = axiMaster.axiMasterClass('tb', Monitors, 'mst1_', '', 'MB')
mc = axiMaster.axiMasterClass('tb', Monitors, 'mst2_', '', 'MC')
md = axiMaster.axiMasterClass('tb', Monitors, 'mst3_', '', 'MD')
slvs = []
for II in range(16):
    if (II != 9):
        slvs.append(
            axiSlave.axiSlaveClass('tb', Monitors, 'slv%s_' % II, '',
                                   'SLV%d' % II))

import sequenceClass


def sequence(TestName):
    Seq = logs.bin2string(TestName)
コード例 #2
0
import os, sys, string, random
import veri
import math
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs
Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 1000  # how many cycles to run before retirment.

import axiMaster
import sequenceClass

axi = axiMaster.axiMasterClass('tb', -1)
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('axi', axi)], {})

Expecteds = [0]


def axi_clk():
    axi.run()
    if veri.peek('tb.wvalid') == '1':
        wdata = logs.peek('tb.wdata')
        Expecteds[-1] += int(math.sqrt(wdata))
        wlast = logs.peek('tb.wlast')
        if wlast == 1:
            Expecteds.append(0)


def pclk():
    if veri.peek('tb.pready') == '0':
コード例 #3
0
import os, sys, string, random, types
import veri

NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs' % NewName)
import logs

Monitors = []
cycles = 0

import antClass
import axiMaster

axi = axiMaster.axiMasterClass('tb', Monitors)
axi.wait(150)
#  def makeWrite(self,Burst,Len,Address,Size=4):
axi.makeWrite(2, 2, 0x6808, 4)
axi.wait(150)
axi.makeRead(2, 2, 0x6808, 4)

import monitorNoc

monnoc = monitorNoc.monitorNocClass(
    'tb.dut',
    'net5@cpu->sw net6@sw0->admin net7@sw1->ant7 net9@dbg->axi net10@axi->ant8 [email protected] [email protected]',
    Monitors)
monnoc.more('net2@ant2->ant3 net3_ant4@ant3->ant4 net4@ant4->cpu')
monnoc.more('net1_ant1@ant1->clk net1_ant2@clk->ant2  net0@admin->ant1')


def negedgea():
コード例 #4
0
probe = axiProbe.axiProbeClass('tb.dut', Auxs, 'merger0_splitter0_', 'MtoS')
probe0 = axiProbe.axiProbeClass('tb.dut', Auxs, 'slv0_', 'SLV0')

import axiMaster
import axiSlave
import panics
import counts

slvs = []
msts = []
for II in range(4):
    slvs.append(
        axiSlave.axiSlaveClass('tb', Monitors, 'slv%s_' % II, '',
                               'SLV%d' % II))
    msts.append(
        axiMaster.axiMasterClass('tb', Monitors, 'mst%s_' % II, '',
                                 'MST%d' % II))

import sequenceClass


def sequence(TestName):
    Seq = logs.bin2string(TestName)
    seq.readfile(Seq)
    logs.setVar('sequence', Seq)
    Dir = os.path.dirname(Seq)
    logs.setVar('testsdir', Dir)
    logs.log_info('SEQUENCE %d' % len(seq.Sequence))


def pymonname(Name):
    logs.pymonname(Name)
コード例 #5
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
import panics

drv = driverClass.driverClass('tb',Monitors)


slvs = [0,0,0,0]
II = 0
slvs[0] =  slvs.append(axiSlave.axiSlaveClass('tb',Monitors0,'slv%s_' % II,'','SLV%d' % II))
II = 1
slvs[1] =  slvs.append(axiSlave.axiSlaveClass('tb',Monitors1,'slv%s_' % II,'','SLV%d' % II))
II = 2
slvs[2] =  slvs.append(axiSlave.axiSlaveClass('tb',Monitors,'slv%s_' % II,'','SLV%d' % II))
II = 3
slvs[2] =  slvs.append(axiSlave.axiSlaveClass('tb',Monitors,'slv%s_' % II,'','SLV%d' % II))

mst = axiMaster.axiMasterClass('tb',Monitors,'mst0_','','MST0')
drv.msts = [mst]


seq = sequenceClass.sequenceClass('tb',Monitors,'',[('drv',drv),('mst0',mst)])


def pymonname(Name):
    logs.pymonname(Name)



def sequence(TestName):
    Seq = logs.bin2string(TestName)
    seq.readfile(Seq)
    logs.setVar('sequence',Seq)
コード例 #6
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff

import os,sys,string,random
import veri
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3'%NewName)
import logs
Monitors=[]
cycles=0
GIVEUP_TIMEOUT = 1000    # how many cycles to run before retirment. 


import axiMaster

mst = axiMaster.axiMasterClass('tb',Monitors,'','','MST')


import sequenceClass
seq = sequenceClass.sequenceClass('tb',Monitors,'',[('mst',mst)])


def pymonname(Name):
    logs.pymonname(Name)



def sequence(TestName):
    Seq = logs.bin2string(TestName)
    seq.readfile(Seq)
    logs.setVar('sequence',Seq)
    Dir = os.path.dirname(Seq)
コード例 #7
0
import os, sys, string, random
import veri
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs
Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 10000  # how many cycles to run before retirment.

import axiMaster
import axiSlave

ma = axiMaster.axiMasterClass('tb', Monitors, 'a_', '', 'MA')
mb = axiMaster.axiMasterClass('tb', Monitors, 'b_', '', 'MB')
mc = axiMaster.axiMasterClass('tb', Monitors, 'c_', '', 'MC')
md = axiMaster.axiMasterClass('tb', Monitors, 'd_', '', 'MD')

slv = axiSlave.axiSlaveClass('tb', Monitors, '', '', 'SLV')

import sequenceClass
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('ma', ma), ('mb', mb),
                                                       ('mc', mc), ('md', md),
                                                       ('slv', slv)])


def pymonname(Name):
    logs.pymonname(Name)


def sequence(TestName):
    Seq = logs.bin2string(TestName)