def __init__(self, name='Fpga', description='Container for FPGA registers', **kwargs): super().__init__(name=name, description=description, **kwargs) self.add( pcie.AxiPcieCore( offset=0x00000000, numDmaLanes=args.numLane, expand=False, )) for i in range(4): self.add( axi.AxiMemTester( name=f'AxiMemTester[{i}]', offset=0x00100000 + i * 0x10000, expand=False, )) self.add(pcie.AxiPipCore( offset=0x00200000, expand=False, ))
def __init__(self,name='Fpga',**kwargs): pr.Device.__init__(self,name=name,**kwargs) self.add(axipcie.AxiPcieCore(useSpi=True)) self.add(surf.protocols.ssi.SsiPrbsTx(name=f'PrbsTx',offset=0x00800000)) self.add(surf.protocols.ssi.SsiPrbsRx(name=f'PrbsRx',offset=0x00900000)) self.add(axipcie.AxiGpuAsyncCore(offset=0x00A00000))
def __init__( self, name = "pciServer", description = "DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) ################################################################# self.dmaStream = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsRx = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbTx = [[None for x in range(args.numVc)] for y in range(args.numLane)] # DataDev PCIe Card if ( args.type == 'pcie' ): # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) # Create the DMA loopback channel for lane in range(args.numLane): for vc in range(args.numVc): self.dmaStream[lane][vc] = rogue.hardware.axi.AxiStreamDma(args.dev,(0x100*lane)+vc,1) # VCS simulation elif ( args.type == 'sim' ): self.memMap = rogue.interfaces.memory.TcpClient('localhost',8000) # Create the DMA loopback channel for lane in range(args.numLane): for vc in range(args.numVc): self.dmaStream[lane][vc] = rogue.interfaces.stream.TcpClient('localhost',8002+(512*lane)+2*vc) # Undefined device type else: raise ValueError("Invalid type (%s)" % (args.type) ) # Add the PCIe core device to base self.add(pcie.AxiPcieCore( memBase = self.memMap, offset = 0x00000000, numDmaLanes = args.numLane, expand = True, )) for lane in range(args.numLane): for vc in range(args.numVc): # Connect the SW PRBS Receiver module self.prbsRx[lane][vc] = pr.utilities.prbs.PrbsRx(name=('SwPrbsRx[%d][%d]'%(lane,vc)),expand=True) self.dmaStream[lane][vc] >> self.prbsRx[lane][vc] self.add(self.prbsRx[lane][vc]) # Connect the SW PRBS Transmitter module self.prbTx[lane][vc] = pr.utilities.prbs.PrbsTx(name=('SwPrbsTx[%d][%d]'%(lane,vc)),expand=True) self.prbTx[lane][vc] >> self.dmaStream[lane][vc] self.add(self.prbTx[lane][vc])
def __init__(self, numDmaLanes=2, numTimingLanes=1, numPgpLanes=1, pgp3=False, **kwargs): super().__init__(**kwargs) self.add( pcie.AxiPcieCore( offset=0x0000_0000, numDmaLanes=numDmaLanes, expand=False, ))
def __init__(self, numLanes=8, pgp3=False, enLclsI=True, enLclsII=False, **kwargs): super().__init__(**kwargs) # Core Layer self.add( pcie.AxiPcieCore( offset=0x0000_0000, numDmaLanes=numLanes, expand=False, ))
def __init__(self, name='Fpga', **kwargs): pr.Device.__init__(self, name=name, **kwargs) self.add(axipcie.AxiPcieCore(useSpi=True)) for i in range(4): self.add( surf.protocols.ssi.SsiPrbsTx(name=f'PrbsTx[{i}]', offset=0x00800000 + (i * 0x100000))) for i in range(4): self.add( surf.protocols.ssi.SsiPrbsRx(name=f'PrbsRx[{i}]', offset=0x00800000 + ((i + 4) * 0x100000)))
def __init__(self, name="XilinxKcu1500Pgp3", description="Container for application registers", **kwargs): super().__init__(name=name, description=description, **kwargs) # Add axi-pcie-core self.add(pcie.AxiPcieCore( offset=0x00000000, expand=False, )) # Add PGP Core for i in range(8): self.add( pgp.Pgp3AxiL( name=('Lane[%i]' % i), offset=(0x00800000 + i * 0x00010000), numVc=4, # 4 VC per lane writeEn=True, expand=False, ))
def __init__(self, name="Pcie", description="Container for FPGA", dev='/dev/datadev_0', hwEmu=False, **kwargs): super().__init__(name=name, description=description, **kwargs) ###################################################################### # Check if emulating the GUI interface if (hwEmu): # Create emulated hardware interface print("Running in Hardware Emulation Mode:") srp = pyrogue.interfaces.simulation.MemEmulate() else: # Create the stream interface memMap = rogue.hardware.axi.AxiMemMap(dev) ###################################################################### self.add( pcie.AxiPcieCore( memBase=memMap, offset=0x00000000, expand=False, )) for i in range(8): self.add( pgp.Pgp3AxiL( memBase=memMap, name=('Pgp3Mon[%d]' % i), offset=(0x00800000 + i * 0x10000), numVc=16, writeEn=True, expand=False, ))
def __init__(self, name="Core", description="Container for SmurfKcu1500RssiOffload10GbE", **kwargs): super().__init__(name=name, description=description, **kwargs) self.add( pcie.AxiPcieCore( offset=0x00000000, numDmaLanes=6, expand=True, )) self.add(EthPhyGrp( offset=0x00860000, expand=True, )) self.add(UdpGrp( offset=0x00800000, expand=True, )) self.add(UdpBufferGrp( offset=0x00870000, expand=True, )) @self.command( name="C_RestartConn", description="Restart connection request", ) def C_RestartConn(): for i in range(6): self.UdpGrp.RssiClient[i].C_RestartConn() ##############################################################################
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) self.perf = args.perf if (self.perf is False): self.dmaStream = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsRx = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsTx = [[None for x in range(args.numVc)] for y in range(args.numLane)] # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, expand=False, )) if (self.perf is True): self.add( ssi.SsiPrbsTx( offset=(0x0040_0000 + 1 * 0x1_0000), memBase=self.memMap, expand=True, )) self.add(
def __init__(self, dataEn=True): pr.Root.__init__(self, name='RateTestDev', description='Rate Tester') # Local map self._dataMap = rogue.hardware.axi.AxiMemMap('/dev/datadev_0') self.add(axipcie.AxiPcieCore(memBase=self._dataMap, useSpi=True)) # PGP Card registers #self.add(XilinxKcu1500Pgp2b(name='HW',memBase=dataMap)) self._pgpVc = {} self._prbsRx = {} self._prbsTx = {} for i in range(4): self._prbsTx[i] = surf.protocols.ssi.SsiPrbsTx( name="prbsTx[{}]".format(i), memBase=self._dataMap, offset=0x00800000 + (i * 0x100000)) self.add(self._prbsTx[i]) if dataEn: self._pgpVc[i] = rogue.hardware.axi.AxiStreamDma( '/dev/datadev_0', i * 256, True) self._prbsRx[i] = pyrogue.utilities.prbs.PrbsRx( name="prbsRx[{}]".format(i), width=256) self.add(self._prbsRx[i]) pyrogue.streamConnect(self._pgpVc[i], self._prbsRx[i]) if dataEn: self.add(PrbsSummary(tx=self._prbsTx, rx=self._prbsRx)) # Start the system self.start(pollEn=True)
required=True, help="path to secondary MCS file", ) # Get the arguments args = parser.parse_args() ################################################################# # Set base base = pr.Root(name='PcieTop', description='') # Create the stream interface memMap = rogue.hardware.axi.AxiMemMap(args.dev) # Add Base Device base.add(pcie.AxiPcieCore(memBase=memMap, useSpi=True)) # Start the system base.start(pollEn=False) # Load the primary MCS file to QSPI[0] base.AxiPcieCore.AxiMicronN25Q[0].LoadMcsFile(args.mcs_pri) # Load the secondary MCS file to QSPI[1] base.AxiPcieCore.AxiMicronN25Q[1].LoadMcsFile(args.mcs_sec) # Close out base.stop() exit()
def __init__( self, name='FmcDev', description='Container for Fmc Dev', hwType='eth', # Define whether sim/rce/pcie/eth HW config ip='192.168.2.10', dev='/dev/datadev_0', # path to device pllConfig='config/pll-config/Si5345-RevD-Registers-160MHz.csv', fullRate=True, # For simulation: True=1.28Gb/s, False=160Mb/s pollEn=True, # Enable automatic polling registers initRead=True, # Read all registers at start of the system fmcFru=False, # True if configuring the FMC's FRU testPattern=False, **kwargs): super().__init__(name=name, description=description, **kwargs) self._dmaSrp = None self._dmaCmd = [None for i in range(4)] self._dmaData = [None for i in range(4)] self._frameGen = [None for lane in range(5)] self._printFrame = [None for lane in range(4)] self.fmcFru = fmcFru self.pllConfig = pllConfig self.hwType = hwType self.testPattern = True if hwType == 'sim' else testPattern # Set the timeout self._timeout = 1.0 # 1.0 default # Start up flags self._pollEn = pollEn self._initRead = initRead # Check for HW type if (hwType == 'eth'): # Connected to FW DMA.Lane[0] self.rudpData = pr.protocols.UdpRssiPack( host=ip, port=8192, packVer=2, ) self.rudpData.locMaxBuffers( 64 ) # Set the SW RSSI buffer to 64 buffers (instead of default=32) self.add(self.rudpData ) # Add the RSSI protocol to the GUI's device tree # Connected to FW DMA.Lane[1] self.rudpSrp = pr.protocols.UdpRssiPack( host=ip, port=8193, packVer=2, ) self.rudpSrp.locMaxBuffers( 64 ) # Set the SW RSSI buffer to 64 buffers (instead of default=32) self.add( self.rudpSrp) # Add the RSSI protocol to the GUI's device tree # SRPv3 on DMA.Lane[1] self._dmaSrp = self.rudpSrp.application(0) for i in range(4): # CMD on DMA.Lane[0].VC[3:0] self._dmaCmd[i] = self.rudpData.application(i + 0) # DATA on DMA.Lane[0].VC[7:4] self._dmaData[i] = self.rudpData.application(i + 4) elif (hwType == 'sim'): # FW/SW co-simulation self.memMap = rogue.interfaces.memory.TcpClient('localhost', 8000) # Set the timeout self._timeout = 100.0 # firmware simulation slow and timeout base on real time (not simulation time) # Start up flags self._pollEn = False self._initRead = False # SRPv3 on DMA.Lane[1] self._dmaSrp = rogue.interfaces.stream.TcpClient( 'localhost', 8002 + (512 * 1) + 2 * 0) for i in range(4): # CMD on DMA.Lane[0].VC[3:0] self._dmaCmd[i] = rogue.interfaces.stream.TcpClient( 'localhost', 8002 + (512 * 0) + 2 * (i + 0)) # DATA on DMA.Lane[0].VC[7:4] self._dmaData[i] = rogue.interfaces.stream.TcpClient( 'localhost', 8002 + (512 * 0) + 2 * (i + 4)) elif (hwType == 'pcie'): # BAR0 access self.memMap = rogue.hardware.axi.AxiMemMap(dev) # Add the PCIe core device to base self.add( pcie.AxiPcieCore( memBase=self.memMap, offset=0x00000000, numDmaLanes=2, expand=False, )) # SRPv3 on DMA.Lane[1] self._dmaSrp = rogue.hardware.axi.AxiStreamDma( dev, (0x100 * 1) + 0, True) for i in range(4): # CMD on DMA.Lane[0].VC[3:0] self._dmaCmd[i] = rogue.hardware.axi.AxiStreamDma( dev, (0x100 * 0) + i + 0, True) # DATA on DMA.Lane[0].VC[7:4] self._dmaData[i] = rogue.hardware.axi.AxiStreamDma( dev, (0x100 * 0) + i + 4, True) elif (hwType == 'rce'): # Create the mmap interface memMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap') # Add RCE version device self.add(rce.RceVersion( memBase=memMap, expand=False, )) # SRPv3 on DMA.Lane[1] self._dmaSrp = rogue.hardware.axi.AxiStreamDma( '/dev/axi_stream_dma_1', 0, True) for i in range(4): # CMD on DMA.Lane[0].VC[3:0] self._dmaCmd[i] = rogue.hardware.axi.AxiStreamDma( '/dev/axi_stream_dma_0', i + 0, True) # DATA on DMA.Lane[0].VC[7:4] self._dmaData[i] = rogue.hardware.axi.AxiStreamDma( '/dev/axi_stream_dma_0', i + 4, True) else: raise ValueError( f'Invalid hwType. Must be either [sim,rce,pcie,eth]') # Connect the DMA SRPv3 stream self._srp = rogue.protocols.srp.SrpV3() pr.streamConnectBiDir(self._dmaSrp, self._srp) # Check if doing test patterns if self.testPattern: # Create the frame generator self._frameGen[4] = LoadSimConfig(fullRate) # Connect the frame generator to "broadcast the Cmd from SW to all the MiniDP ports" pr.streamConnect(self._frameGen[4], self._dmaData[0]) # DMA.Lane[0].VC[4].TX for i in range(4): # Create the frame generator self._frameGen[i] = LoadSimConfig(fullRate) self._printFrame[i] = PrintSlaveStream() # Connect the frame generator pr.streamConnect(self._frameGen[i], self._dmaCmd[i]) # DMA.Lane[0].VC[3:0].TX pr.streamConnect(self._dmaData[i], self._printFrame[i]) # DMA.Lane[0].VC[7:4].RX # Create a command to execute the frame generator self.add( pr.BaseCommand( name=f'SimConfig[{i}]', function=lambda cmd, i=i: self._frameGen[i].config(), )) self.add( pr.BaseCommand( name=f'SimScan[{i}]', function=lambda cmd, i=i: [ self.CountReset(), self._printFrame[i].cntRst(), self._frameGen[i].scan() ], )) # self.add(pr.BaseCommand( # name = f'SimCntRst[{i}]', # function = lambda cmd, i=i: self._printFrame[i].cntRst(), # )) # FMC Board self.add( hw.Fmc( memBase=self._srp, simulation=(hwType == 'sim'), fmcFru=fmcFru, expand=True, )) # Start the system self.start( pollEn=self._pollEn, initRead=self._initRead, timeout=self._timeout, )
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) if (args.swRx or args.swTx): self.dmaStream = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsRx = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsTx = [[None for x in range(args.numVc)] for y in range(args.numLane)] # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, boardType=args.boardType, expand=True, )) # Add PGP Core for lane in range(args.numLane): if (args.version == 4): self.add( pgp.Pgp4AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=True, )) elif (args.version == 3): self.add( pgp.Pgp3AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000 + 0x1000), memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpTxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x3000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpRxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x4000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) # Loop through the virtual channels for vc in range(args.numVc): if (args.swRx or args.swTx): self.dmaStream[lane][vc] = rogue.hardware.axi.AxiStreamDma( args.dev, (0x100 * lane) + vc, 1) if (args.swRx): # Connect the SW PRBS Receiver module self.prbsRx[lane][vc] = pr.utilities.prbs.PrbsRx( name=('SwPrbsRx[%d][%d]' % (lane, vc)), width=args.prbsWidth, checkPayload=True, expand=False, ) self.dmaStream[lane][vc] >> self.prbsRx[lane][vc] self.add(self.prbsRx[lane][vc]) if (args.swTx): # Connect the SW PRBS Transmitter module self.prbsTx[lane][vc] = pr.utilities.prbs.PrbsTx( name=('SwPrbsTx[%d][%d]' % (lane, vc)), width=args.prbsWidth, expand=False, ) self.prbsTx[lane][vc] >> self.dmaStream[lane][vc] self.add(self.prbsTx[lane][vc]) @self.command() def EnableAllSwTx(): swTxDevices = root.find(typ=pr.utilities.prbs.PrbsTx) for tx in swTxDevices: tx.txEnable.set(True) @self.command() def DisableAllSwTx(): swTxDevices = root.find(typ=pr.utilities.prbs.PrbsTx) for tx in swTxDevices: tx.txEnable.set(False)
def __init__(self, dev, **kwargs): super().__init__(**kwargs) memMap = rogue.hardware.axi.AxiMemMap(dev) self.add(pcie.AxiPcieCore(memBase=memMap, useBpi=True, useSpi=True))
import lcls2_timetool class TimeToolKcu1500(pr.Device): def __init__(self, numLanes=1, pgp3=False, **kwargs): super().__init__(**kwargs) # The time tool application self.add(lcls2_timetool.Application( offset = 0x00C0_0000, numLanes = numLanes)) # PGP Hardware on PCIe self.add(lcls2_pgp_fw_lib.hardware.XilinxKcu1500.Kcu1500Hsio( offset = 0x0080_0000, numLanes = numLanes, enLclsI = False, enLclsII = True, pgp3 = pgp3, expand = True, )) self.add(axipcie.AxiPcieCore( offset = 0x00000000, numDmaLanes = numLanes, expand = False, ))
def __init__(self, name="Hardware", description="Container for PCIe Hardware Registers", numLane=4, version3=False, **kwargs): super().__init__(name=name, description=description, **kwargs) # Add axi-pcie-core self.add( pcie.AxiPcieCore( offset=0x00000000, numDmaLanes=numLane, expand=False, )) # Add PGP Core for i in range(numLane): if (version3): self.add( pgp.Pgp3AxiL( name=(f'PgpMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 0 * 0x2000), numVc=4, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=(f'PgpMon[{i}]'), offset=(0x00800000 + i * 0x00010000), writeEn=True, expand=False, )) self.add( axi.AxiStreamMonitoring( name=(f'PgpTxAxisMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 1 * 0x2000), numberLanes=4, expand=False, )) self.add( axi.AxiStreamMonitoring( name=(f'PgpRxAxisMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 2 * 0x2000), numberLanes=4, expand=False, )) # Add Timing Core self.add( XilinxKcu1500Pgp.Timing( offset=0x00900000, numLane=numLane, expand=False, ))
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, boardType=args.boardType, expand=True, )) # Add PGP Core for lane in range(args.numLane): if (args.version == 4): self.add( pgp.Pgp4AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=True, )) elif (args.version == 3): self.add( pgp.Pgp3AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000 + 0x1000), memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpTxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x3000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpRxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x4000), numberLanes=args.numVc, memBase=self.memMap, expand=False, ))
def __init__(self, name="Top", description="Container for FEB FPGA", dev='/dev/datadev_0', hwType='pcie', ip='10.0.0.1', **kwargs): super().__init__(name=name, description=description, **kwargs) # File writer dataWriter = pr.utilities.fileio.StreamWriter() self.add(dataWriter) ###################################################################### if (hwType == 'hsio-dtm') or (hwType == 'rce-dpm'): # Create the mmap interface rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap') # Add RCE version device self.add(rceg3.RceVersion( memBase=rceMap, expand=False, )) # Add PGPv3 to the FEB self.add( pgp.Pgp3AxiL( name='Pgp3Mon', memBase=rceMap, offset=0xA0000000, numVc=1, writeEn=True, expand=False, )) if (hwType == 'hsio-dtm'): # Add PGPv2b to the HSIO FPGA self.add( pgp.Pgp2bAxi( name='Pgp2bMon', memBase=rceMap, offset=0xA1000000, expand=False, )) # Connect the SRPv0 to PGPv2b.VC[1] pgp2bVc1 = rogue.hardware.axi.AxiStreamDma( '/dev/axi_stream_dma_0', 1, True) srpV0 = rogue.protocols.srp.SrpV0() pr.streamConnectBiDir(srpV0, pgp2bVc1) if (hwType == 'pcie'): axiMemMap = rogue.hardware.axi.AxiMemMap(dev) self.add( pcie.AxiPcieCore( memBase=axiMemMap, offset=0x00000000, expand=False, )) # for i in range(8): # self.add(pgp.Pgp3AxiL( # memBase = axiMemMap, # name = ('Pgp3Mon[%d]' % i), # offset = (0x00800000 + i*0x10000), # numVc = 16, # writeEn = True, # expand = False, # )) ###################################################################### # Create an empty stream arrays configStream = [None] * 4 dataStream = [None] * 4 ######################################################################################################################## # https://github.com/slaclab/rogue/blob/master/include/rogue/hardware/axi/AxiStreamDma.h # static boost::shared_ptr<rogue::hardware::axi::AxiStreamDma> create (std::string path, uint32_t dest, bool ssiEnable); ######################################################################################################################## ###################################################################### # PGPv3.[VC=0] = FEB SRPv3 Register Access # PGPv3.[VC=1] = RD53[DPORT=0] Streaming ASIC Configuration Interface # PGPv3.[VC=2] = RD53[DPORT=1] Streaming ASIC Configuration Interface # PGPv3.[VC=3] = RD53[DPORT=2] Streaming ASIC Configuration Interface # PGPv3.[VC=4] = RD53[DPORT=3] Streaming ASIC Configuration Interface # PGPv3.[VC=5] = RD53[DPORT=0] Streaming Data Interface # PGPv3.[VC=6] = RD53[DPORT=1] Streaming Data Interface # PGPv3.[VC=7] = RD53[DPORT=2] Streaming Data Interface # PGPv3.[VC=8] = RD53[DPORT=3] Streaming Data Interface ###################################################################### if (hwType == 'simulation'): srpStream = pr.interfaces.simulation.StreamSim(host='localhost', dest=0, uid=12, ssi=True) for i in range(4): configStream[i] = pr.interfaces.simulation.StreamSim( host='localhost', dest=1 + i, uid=12, ssi=True) dataStream[i] = pr.interfaces.simulation.StreamSim( host='localhost', dest=5 + i, uid=12, ssi=True) elif (hwType == 'eth'): rudp = pr.protocols.UdpRssiPack(host=ip, port=8192, packVer=2) srpStream = rudp.application(0) for i in range(4): configStream[i] = rudp.application(1 + i) dataStream[i] = rudp.application(5 + i) else: srpStream = rogue.hardware.axi.AxiStreamDma(dev, 0, True) for i in range(4): configStream[i] = rogue.hardware.axi.AxiStreamDma( dev, 1 + i, True) dataStream[i] = rogue.hardware.axi.AxiStreamDma( dev, 5 + i, True) ###################################################################### # Connect the SRPv3 to PGPv3.VC[0] memMap = rogue.protocols.srp.SrpV3() pr.streamConnectBiDir(memMap, srpStream) for i in range(4): # Add data stream to file as channel [i] to dataStream[i] pr.streamConnect(dataStream[i], dataWriter.getChannel(i)) ###################################################################### # Add devices self.add( axiVer.AxiVersion( name='AxiVersion', memBase=memMap, offset=0x00000000, expand=False, )) self.add( xil.Xadc( name='Xadc', memBase=memMap, offset=0x00010000, expand=False, )) self.add( prom.AxiMicronP30( name='AxiMicronP30', memBase=memMap, offset=0x00020000, hidden=True, # Hidden in GUI because indented for scripting )) self.add( common.SysReg( name='SysReg', description= 'This device contains system level configuration and status registers', memBase=memMap, offset=0x00030000, expand=False, )) self.add( common.Ntc( name='Rd53Ntc', description= 'This device contains the four NTC MAX6682 readout modules', memBase=memMap, offset=0x00040000, expand=False, )) self.add( nxp.Sa56004x( name='BoardTemp', description= 'This device monitors the board temperature and FPGA junction temperature', memBase=memMap, offset=0x00050000, expand=False, )) self.add( linear.Ltc4151( name='BoardPwr', description= 'This device monitors the board power, input voltage and input current', memBase=memMap, offset=0x00050400, senseRes=20.E-3, # Units of Ohms expand=False, )) for i in range(4): self.add( common.RxPhyMon( name=('RxPhyMon[%d]' % i), memBase=memMap, offset=(0x01000000 * (i + 1) + 0x00100000), expand=False, )) self.add( common.Timing( name='Timing', description= 'This device monitors the TLU and timing/trigger emulator', memBase=memMap, offset=0x05000000, expand=False, ))
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create an arrays to be filled self.dmaStream = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsRx = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbTx = [[None for x in range(args.numVc)] for y in range(args.numLane)] # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev, ) # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, expand=True, )) for i in range(4): self.add( axi.AxiMemTester( name=f'AxiMemTester[{i}]', offset=0x0010_0000 + i * 0x1_0000, memBase=self.memMap, expand=True, )) # Loop through the DMA channels for lane in range(args.numLane): # Loop through the virtual channels for vc in range(args.numVc): if (args.fwTx): # Add the FW PRBS TX Module self.add( ssi.SsiPrbsTx( name=('FwPrbsTx[%d][%d]' % (lane, vc)), memBase=self.memMap, offset=0x00800000 + (0x10000 * lane) + (0x1000 * (2 * vc + 0)), expand=False, )) if (args.fwRx): # Add the FW PRBS RX Module self.add( ssi.SsiPrbsRx( name=('FwPrbsRx[%d][%d]' % (lane, vc)), memBase=self.memMap, offset=0x00800000 + (0x10000 * lane) + (0x1000 * (2 * vc + 1)), expand=False, )) # Loop through the DMA channels for lane in range(args.numLane): # Loop through the virtual channels for vc in range(args.numVc): # Set the DMA loopback channel self.dmaStream[lane][vc] = rogue.hardware.axi.AxiStreamDma( args.dev, (0x100 * lane) + vc, 1) # self.dmaStream[lane][vc].setDriverDebug(0) if (args.loopback): # Loopback the PRBS data self.dmaStream[lane][vc] >> self.dmaStream[lane][vc] else: if (args.swRx): # Connect the SW PRBS Receiver module self.prbsRx[lane][vc] = pr.utilities.prbs.PrbsRx( name=('SwPrbsRx[%d][%d]' % (lane, vc)), width=args.prbsWidth, checkPayload=False, expand=True, ) self.dmaStream[lane][vc] >> self.prbsRx[lane][vc] self.add(self.prbsRx[lane][vc]) if (args.swTx): # Connect the SW PRBS Transmitter module self.prbTx[lane][vc] = pr.utilities.prbs.PrbsTx( name=('SwPrbsTx[%d][%d]' % (lane, vc)), width=args.prbsWidth, expand=False, ) self.prbTx[lane][vc] >> self.dmaStream[lane][vc] self.add(self.prbTx[lane][vc]) @self.command() def EnableAllFwTx(): fwTxDevices = root.find(typ=ssi.SsiPrbsTx) for tx in fwTxDevices: tx.TxEn.set(True) @self.command() def DisableAllFwTx(): fwTxDevices = root.find(typ=ssi.SsiPrbsTx) for tx in fwTxDevices: tx.TxEn.set(False)