class TestSimS2C(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.path.dirname(__file__) + '/test_SimI2c.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_i2c(self):
data = [0x85, 0x81, 0xa5, 0x91]
self.chip['i2c'].write(0x92, data)
ret = self.chip['i2c'].get_data(4)
self.assertEqual(ret.tolist(), data)
self.chip['i2c'].write(0x92, data[0:1])
self.chip['i2c'].set_data([0, 1, 2, 3])
ret = self.chip['i2c'].read(0x92, 3)
self.assertEqual(ret.tolist(), data[1:])
# no ack/no such device
exept = False
try:
self.chip['i2c'].write(0x55, data)
except IOError:
exept = True
self.assertEqual(exept, True)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def setUp(self):
sys.path = [os.path.dirname(os.getcwd())] + sys.path
proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
cocotb_compile_and_run(
sim_files = [proj_dir + '/test/mmc3_eth_tb.v'],
top_level = 'tb',
include_dirs = (proj_dir, proj_dir + '/src')
)
'''
with open("test_mmc3_eth.yaml") as conf_file:
try:
conf = yaml.load(conf_file)
except yaml.YAMLError as exception:
print(exception)
conf['transfer_layer'][0]['type']
self.chip = Dut(conf)
self.chip.init()
'''
self.chip = Dut(cnfg_yaml)
self.chip.init()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__),
'../firmware/src/sram_test.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')
],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver')
with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'),
'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
cocotb_compile_and_run(['test_SimTlu.v'])
cnfg = yaml.load(cnfg_yaml)
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
sys.path = [os.path.dirname(os.getcwd())] + sys.path
proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
cocotb_compile_and_run(
sim_files=[proj_dir + '/test/bdaq53_eth_tb.v'],
top_level='tb',
include_dirs=(proj_dir, proj_dir + '/firmware/src')
)
with open(proj_dir + '/bdaq53_eth.yaml') as conf_file:
try:
conf = yaml.safe_load(conf_file)
except yaml.YAMLError as exception:
print(exception)
conf['transfer_layer'][0]['type'] = 'SiSim'
conf['transfer_layer'][0]['tcp_connection'] = 'False'
# conf['hw_drivers']['FIFO'] = ({'name': 'fifo',
# 'type': 'sram_fifo',
# 'interface': 'intf',
# 'base_addr': 0x8000,
# 'base_data_addr': 0x80000000})
conf['hw_drivers'].append({'name': 'FIFO', 'type': 'sram_fifo',
'interface': 'intf', 'base_addr': 0x8000, 'base_data_addr': 0x80000000})
self.chip = Dut(conf)
self.chip.init()
class TestSimS2C(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimI2c.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_i2c(self):
data = [0x85, 0x81, 0xa5, 0x91]
self.chip['i2c'].write(0x92, data)
ret = self.chip['i2c'].get_data(4)
self.assertEqual(ret.tolist(), data)
self.chip['i2c'].write(0x92, data[0:1])
self.chip['i2c'].set_data([0, 1, 2, 3])
ret = self.chip['i2c'].read(0x92, 3)
self.assertEqual(ret.tolist(), data[1:])
# no ack/no such device
exept = False
try:
self.chip['i2c'].write(0x55, data)
except IOError:
exept = True
self.assertEqual(exept, True)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run(
[os.path.join(os.path.dirname(__file__), 'test_SimGpio.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
self.chip['GPIO'].set_output_en([0xff, 0,
0]) # to remove 'z in simulation
ret = self.chip['GPIO'].get_data()
self.assertEqual([0, 0, 0], ret)
self.chip['GPIO'].set_output_en([0x0f, 0, 0])
self.chip['GPIO'].set_data([0xe3, 0xfa, 0x5a])
ret = self.chip['GPIO'].get_data()
self.assertEqual([0x33, 0x5a, 0x5a], ret)
ret = self.chip['GPIO2'].get_data()
self.assertEqual([0xa5, 0xcd], ret)
def test_io_register(self):
self.chip['GPIO'].set_output_en([0xff, 0,
0]) # to remove 'z in simulation
self.chip['GPIO']['OUT'] = 0xa5
self.chip['GPIO'].write()
ret = self.chip['GPIO'].get_data()
self.assertEqual([0, 0xa5, 0xa5], ret)
# TODO: Add register readback and comparison
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def setUp(self):
cocotb_compile_and_run([
os.path.join(os.path.dirname(__file__), 'test_SimTimestampDiv.v')
])
self.chip = Dut(cnfg_yaml)
self.chip.init()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimGpio.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0, 0], ret)
self.chip['gpio'].set_data([0xe3, 0xfa, 0x5a])
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0x5a, 0x5a], ret)
self.chip['gpio'].set_output_en([0x0f, 0, 0])
ret = self.chip['gpio'].get_data()
self.assertEqual([0x33, 0x5a, 0x5a], ret)
def test_io_register(self):
self.chip['GPIO']['OUT'] = 0xa5
self.chip['GPIO'].write()
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0xa5, 0xa5], ret)
# TODO: Add register readback and comparison
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimGpio.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0, 0], ret)
self.chip['gpio'].set_data([0xe3, 0xfa, 0x5a])
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0x5a, 0x5a], ret)
self.chip['gpio'].set_output_en([0x0f, 0, 0])
ret = self.chip['gpio'].get_data()
self.assertEqual([0x33, 0x5a, 0x5a], ret)
def test_io_register(self):
self.chip['GPIO']['OUT'] = 0xa5
self.chip['GPIO'].write()
ret = self.chip['gpio'].get_data()
self.assertEqual([0, 0xa5, 0xa5], ret)
# TODO: Add register readback and comparison
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimTlu(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run(
[os.path.join(os.path.dirname(__file__), 'test_SimTdc.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_tdc(self):
self.chip['TDC'].ENABLE = 1
self.chip['SEQ'].REPEAT = 1
for index, i in enumerate(range(0, 10)):
length = i + 1
self.chip['SEQ'].SIZE = length + 1
self.chip['SEQ']['TDC_IN'][0:length] = True
self.chip['SEQ'].write(length)
self.chip['SEQ'].START
while (not self.chip['SEQ'].is_ready):
pass
self.assertEqual(self.chip['FIFO'].get_FIFO_INT_SIZE(), 1)
data = self.chip['FIFO'].get_data()
self.assertEqual(data[0], (index << 12) + length)
def test_tdc_overflow(self):
self.chip['TDC'].ENABLE = 1
self.chip['SEQ'].REPEAT = 1
for index, i in enumerate(range(4094, 4097)):
length = i + 1
self.chip['SEQ_GEN'].SIZE = length + 1
self.chip['SEQ']['TDC_IN'][0:length] = True
self.chip['SEQ'].write(length)
self.chip['SEQ'].START
while (not self.chip['SEQ_GEN'].is_ready):
pass
self.assertEqual(self.chip['FIFO'].get_FIFO_INT_SIZE(), 1)
data = self.chip['FIFO'].get_data()
self.assertEqual(data[0], (index << 12) +
min(length, 4095)) # overflow 12bit
# def test_tdc_delay(self):
# pass
#
# def test_tdc_delay_overflow(self):
# pass
#
# def test_tdc_delay_late_trigger(self):
# pass
#
# def test_tdc_arm(self):
# pass
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def __init__(self, conf=None):
if conf is None:
conf = os.path.join(os.path.dirname(os.path.abspath(__file__)),
"m26.yaml")
logger.info("Loading DUT configuration from file %s" % conf)
# initialize class
self.dut = Dut(conf=conf)
def setUp(self):
cocotb_compile_and_run([
os.path.join(os.path.dirname(__file__), 'jtag_tap.v'),
os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v')
])
self.chip = Dut(cnfg_yaml)
self.chip.init(init_yaml)
def setUp(self):
cocotb_compile_and_run(
sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)],
sim_bus=self._sim_bus,
extra_defines=self._bus_split_def)
self.chip = Dut(cnfg_yaml)
self.chip.init()
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimSeq.v'])
cnfg = yaml.load(cnfg_yaml)
self.chip = Dut(cnfg)
self.chip.init()
def __init__(self, debug=False, **kwargs):
self.debug = debug
self.devices = Dut('config.yaml')
if self.debug is False:
self.devices.init()
if kwargs['xray_use_remote'] is True:
self.xraymachine = Dut('xray.yaml')
self.xraymachine.init()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimSpi.v'])
cnfg = yaml.load(cnfg_yaml)
self.chip = Dut(cnfg)
self.chip.init()
def test_io(self):
size = self.chip['spi'].get_size()
self.chip['gpio'].reset()
self.assertEqual(size, 16 * 8)
self.chip['spi'].set_data(range(16))
ret = self.chip['spi'].get_data(size=16,
addr=0) #to read back what was written
self.assertEqual(ret.tolist(), range(16))
self.chip['spi'].set_data(range(16))
ret = self.chip['spi'].get_data(addr=0) #to read back what was written
self.assertEqual(ret.tolist(), range(16))
self.chip['spi'].start()
while (not self.chip['spi'].is_done()):
time.sleep(0.1)
ret = self.chip['spi'].get_data(
) # read back what was received (looped)
self.assertEqual(ret.tolist(), range(16))
#spi_rx
ret = self.chip['spi_rx'].get_en()
self.assertEqual(ret, False)
self.chip['spi_rx'].set_en(True)
ret = self.chip['spi_rx'].get_en()
self.assertEqual(ret, True)
self.chip['spi'].start()
while (not self.chip['spi'].is_done()):
time.sleep(0.1)
ret = self.chip['fifo'].get_fifo_size()
self.assertEqual(ret, 32)
ret = self.chip['fifo'].get_data()
data0 = ret.astype(np.uint8)
data1 = np.right_shift(ret, 8).astype(np.uint8)
data = np.reshape(np.vstack((data1, data0)), -1, order='F')
self.assertEqual(data.tolist(), range(16))
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def setUp(self):
cocotb_compile_and_run(
[
os.path.join(os.path.dirname(__file__), "jtag_tap.v"),
os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v"),
]
)
self.chip = Dut(cnfg_yaml)
self.chip.init(init_yaml)
def test_default(self):
self.cnfg['registers'][1]['fields'][0]['default'] = 0x01 # VINJECT
self.dut = Dut(self.cnfg)
self.dut.init()
mem = dict()
# mem[0] = 0 # reset
mem[8] = 0x08
mem[9] = 0
mem[10] = 0
self.dut['TEST2'].write()
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def __init__(self):
self.dut = Dut(conf)
self.dut.init()
# fw_version = dut['ETH'].read(0x0000, 1)[0]
logging.info("Firmware version: %s" % self.dut['REGISTERS'].VERSION)
signal.signal(signal.SIGINT, self.signal_handler)
logging.info('Press Ctrl-C to stop')
self.stop_thread = Event()
self.total_tcp_err_cnt = 0
class TestSimTimestamp(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run(
[os.path.join(os.path.dirname(__file__), 'test_SimTimestamp.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
self.chip['timestamp'].reset()
self.chip['timestamp']["ENABLE"] = 1
self.chip['gpio'].reset()
self.chip['fifo'].reset()
ret = self.chip['fifo'].get_fifo_size()
self.assertEqual(ret, 0)
# trigger timestamp
self.chip['PULSE_GEN'].set_delay(0x105)
self.chip['PULSE_GEN'].set_width(10)
self.chip['PULSE_GEN'].set_repeat(1)
self.assertEqual(self.chip['PULSE_GEN'].get_delay(), 0x105)
self.assertEqual(self.chip['PULSE_GEN'].get_width(), 10)
self.assertEqual(self.chip['PULSE_GEN'].get_repeat(), 1)
self.chip['PULSE_GEN'].start()
while (not self.chip['PULSE_GEN'].is_done()):
pass
# get data from fifo
ret = self.chip['fifo'].get_fifo_size()
self.assertEqual(ret, 3 * 4)
ret = self.chip['fifo'].get_data()
self.assertEqual(len(ret), 3)
# check with gpio
ret2 = self.chip['gpio'].get_data()
self.assertEqual(len(ret2), 8)
for i, r in enumerate(ret):
self.assertEqual(r & 0xF0000000, 0x50000000)
self.assertEqual(r & 0xF000000, 0x1000000 * (3 - i))
self.assertEqual(ret[2] & 0xFFFFFF,
0x10000 * ret2[5] + 0x100 * ret2[6] + ret2[7])
self.assertEqual(ret[1] & 0xFFFFFF,
0x10000 * ret2[2] + 0x100 * ret2[3] + ret2[4])
self.assertEqual(ret[1] & 0xFFFFFF, 0x100 * ret2[0] + ret2[1])
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def __init__(self, scan_config, device_config=None):
self.config = scan_config
self.run_name = time.strftime("%Y%m%d_%H%M%S") + '_' + self.scan_id
self.output_filename = os.path.join(OUTPUT_DIR,
self.config['module_name'],
self.run_name)
self.log = logging.getLogger(self.__class__.__name__)
if device_config is None:
device_config = os.path.join(
os.path.abspath(os.path.dirname(__file__)), 'sensor_iv.yaml')
self.devices = Dut(device_config)
class TestExampleMIO(unittest.TestCase):
def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/utils/fx2_to_bus.v",
os.path.dirname(__file__) + "/../src/example.v",
],
top_level="example",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/example.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
def test(self):
ret = self.chip["GPIO_LED"].get_data()
self.assertEqual([0], ret)
self.chip["GPIO_LED"]["LED"] = 0x01
self.chip["GPIO_LED"].write()
ret = self.chip["GPIO_LED"].get_data()
self.assertEqual([0x21], ret)
self.chip["GPIO_LED"]["LED"] = 0x02
self.chip["GPIO_LED"].write()
ret = self.chip["GPIO_LED"].get_data()
self.assertEqual([0x42], ret)
self.chip["GPIO_LED"]["LED"] = 0x03
self.chip["GPIO_LED"].write()
ret = self.chip["GPIO_LED"].get_data()
self.assertEqual([0x63], ret)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimAdcRx.v'])
cnfg = yaml.load(cnfg_yaml)
self.chip = Dut(cnfg)
self.chip.init()
def test_io(self):
pattern = [1, 0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7]
self.chip['SEQ_GEN'].set_data(pattern)
self.chip['PULSE_GEN'].set_delay(1)
self.chip['PULSE_GEN'].set_width(1)
self.chip['SEQ_GEN'].set_en_ext_start(True)
self.chip['SEQ_GEN'].set_size(8)
self.chip['SEQ_GEN'].set_repeat(1)
#this is to have something in memory and not X
self.chip['PULSE_GEN'].start()
self.chip['SEQ_GEN'].is_done()
self.chip['SEQ_GEN'].is_done()
while (not self.chip['SEQ_GEN'].is_done()):
pass
#take some data
self.chip['FADC'].set_align_to_sync(True)
self.chip['FADC'].set_data_count(16)
self.chip['FADC'].set_single_data(True)
self.chip['FADC'].start()
self.chip['PULSE_GEN'].start()
self.chip['SEQ_GEN'].is_done()
self.chip['SEQ_GEN'].is_done()
while (not self.chip['FADC'].is_done()):
pass
ret = self.chip['fifo'].get_data()
self.assertEqual(
ret[2:2 + 8].tolist(),
[0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107])
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimM26(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run(
[os.path.join(os.path.dirname(__file__), 'test_SimFifo8to32.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
for i in range(4):
self.chip['INTF'].write(0x1000, [i])
data = []
iterations = 1000
i = 0
while not len(data) == 1:
if i >= iterations:
break
data.extend(self.chip['FIFO'].get_data())
i += 1
assert data[0] == 50462976
self.chip['INTF'].write(0x1000, [4, 5, 6, 7])
data = []
iterations = 1000
i = 0
while not len(data) == 1:
if i >= iterations:
break
data.extend(self.chip['FIFO'].get_data())
i += 1
assert data[0] == 117835012
self.chip['INTF'].write(0x1000, range(8))
data = []
iterations = 1000
i = 0
while not len(data) == 2:
if i >= iterations:
break
data.extend(self.chip['FIFO'].get_data())
i += 1
assert data[0] == 50462976
assert data[1] == 117835012
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestExampleMIO(unittest.TestCase):
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'gpio/gpio_core.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(os.path.dirname(__file__), '../src/example.v')
],
top_level='example',
sim_bus='basil.utils.sim.SiLibUsbBusDriver')
with open(os.path.join(os.path.dirname(__file__), 'example.yaml'),
'r') as f:
cnfg = yaml.safe_load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def test_gpio(self):
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0], ret)
self.chip['GPIO_LED']['LED'] = 0x01
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x21], ret)
self.chip['GPIO_LED']['LED'] = 0x02
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x42], ret)
self.chip['GPIO_LED']['LED'] = 0x03
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x63], ret)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def test_default(self):
self.cnfg['registers'][1]['fields'][0]['default'] = 0x01 # VINJECT
self.dut = Dut(self.cnfg)
self.dut['spi_module']._require_version = "==1"
self.dut.init()
self.dut['spi_module']._mem_bytes = 32
mem = dict()
# mem[0] = 0 # reset
mem[0] = 1
mem[14] = 4
mem[16] = 0x08
mem[17] = 0
mem[18] = 0
self.dut['TEST2'].write()
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def temprature_dose(Directory=False,
Sourcemeter=True,
time_size=100,
delay=2,
CurrentLimit=1.000000E-06):
'''
Assuming that the cabinet door is the -z
x : Number of movements to x direction
z: Number of movements inside the cabinet
Size_x: size of the steps in x direction
'''
t0 = time.time()
if Sourcemeter:
dut = Dut('sensor_sourcemeter_scan_pyserial.yaml')
dut.init()
dut['sm'].write(":OUTP ON")
dut['sm'].write("*RST")
dut['sm'].write(":SOUR:VOLT:RANG 60")
dut['sm'].write('SENS:CURR:PROT ' + str(CurrentLimit))
print "The Protection Current limit is", dut['sm'].ask(
"SENS:CURR:PROT?")
dut['sm'].write(":SOUR:FUNC VOLT")
dut['sm'].write(':SOUR:VOLT 50')
else:
dut = Dut('temprature_scan_pyserial.yaml')
dut.init()
with tb.open_file(Directory + 'temprature_dose.h5', "w") as out_file_h5:
description = np.zeros(
(1, ),
dtype=np.dtype([("time", "f8"), ("current", "f8"),
("temprature", "f8"), ("humidity", "f8"),
("dew", "f8")])).dtype
Data_table = out_file_h5.create_table(out_file_h5.root,
name='temprature_dose',
description=description,
filters=tb.Filters(
complib='blosc',
complevel=5,
fletcher32=False))
read = Data_table.row
for i in xrange(time_size):
t1 = time.time()
read["time"] = t1 - t0
read["temprature"] = dut['ts'].get_temperature()
read["humidity"] = dut['ts'].get_humidity()
read["dew"] = dut['ts'].get_dew_point()
if Sourcemeter:
val = dut['sm'].ask(":MEAS:CURR?")
current = val[15:-43]
else:
current = random.randint(1, 101)
read["current"] = current
read.append()
temp = dut['ts'].get_temperature()
print temp, t1 - t0, current
time.sleep(delay)
Data_table.flush()
out_file_h5.close()
def __init__(self, conf_file_name=None, voltage=1.5, conf_dict=None):
"""
Initializes the chip, including turning on power.
Exactly one of conf_file_name and conf_dict must be specified.
This method also initializes the block lengths to their
appropriate values.
"""
if not (bool(conf_file_name) != bool(conf_dict)):
raise ValueError("conf_file_name xor conf_dict must be specified.")
elif conf_file_name:
# Read in the configuration YAML file
stream = open(conf_file_name, 'r')
conf_dict = yaml.load(stream)
else: # conf_dict must be specified
pass
# Create the T3MAPSDriver object
Dut.__init__(self, conf_dict)
try:
# Initialize the chip
self.init()
except NotImplementedError: # this is to make simulation not fail
print 'chip.init() :: NotImplementedError'
# turn on the adapter card's power
self['PWR']['EN_VD1'] = 1
self['PWR']['EN_VD2'] = 1
self['PWR']['EN_VA1'] = 1
self['PWR']['EN_VA2'] = 1
self['PWR'].write()
# Set the output voltage on the pins
self['PWRAC'].set_voltage("VDDD1", voltage)
self['PWRAC'].set_voltage("VDDD2", voltage)
# Set the "block lengths" for commands to pixel and global registers
self._block_lengths['pixel'] = len(self['PIXEL_REG'])
# 2 extra for load commands, 1 for the 'dropped' bit due to clock
self._block_lengths['global'] = len(self['GLOBAL_REG']) + 2 +\
self._global_dropped_bits
# arbitrary length, but long enough to be detected by discriminator.
self._block_lengths['inject'] = 500
# Make sure the chip is reset
self.reset_seq()
def __init__(self, conf_file_name=None, voltage=1.5, conf_dict=None):
"""
Initializes the chip, including turning on power.
Exactly one of conf_file_name and conf_dict must be specified.
This method also initializes the block lengths to their
appropriate values.
"""
if not (bool(conf_file_name) != bool(conf_dict)):
raise ValueError("conf_file_name xor conf_dict must be specified.")
elif conf_file_name:
# Read in the configuration YAML file
stream = open(conf_file_name, 'r')
conf_dict = yaml.load(stream)
else: # conf_dict must be specified
pass
# Create the T3MAPSDriver object
Dut.__init__(self, conf_dict)
try:
# Initialize the chip
self.init()
except NotImplementedError: # this is to make simulation not fail
print 'chip.init() :: NotImplementedError'
# turn on the adapter card's power
self['PWR']['EN_VD1'] = 1
self['PWR']['EN_VD2'] = 1
self['PWR']['EN_VA1'] = 1
self['PWR']['EN_VA2'] = 1
self['PWR'].write()
# Set the output voltage on the pins
self['PWRAC'].set_voltage("VDDD1", voltage)
self['PWRAC'].set_voltage("VDDD2", voltage)
# Set the "block lengths" for commands to pixel and global registers
self._block_lengths['pixel'] = len(self['PIXEL_REG'])
# 2 extra for load commands, 1 for the 'dropped' bit due to clock
self._block_lengths['global'] = len(self['GLOBAL_REG']) + 2 +\
self._global_dropped_bits
# arbitrary length, but long enough to be detected by discriminator.
self._block_lengths['inject'] = 500
# Make sure the chip is reset
self.reset_seq()
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'),
os.path.join(fw_path, 'utils/ODDR_sim.v'),
os.path.join(fw_path, 'utils/generic_fifo.v'),
os.path.join(fw_path, 'utils/cdc_pulse_sync.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen.v'),
os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
os.path.join(os.path.dirname(__file__), '../firmware/src/sram_test.v'),
os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
top_level='tb',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/rrp_arbiter/rrp_arbiter.v",
fw_path + "/utils/ODDR_sim.v",
fw_path + "/utils/generic_fifo.v",
fw_path + "/utils/cdc_pulse_sync.v",
fw_path + "/utils/fx2_to_bus.v",
fw_path + "/pulse_gen/pulse_gen.v",
fw_path + "/pulse_gen/pulse_gen_core.v",
fw_path + "/sram_fifo/sram_fifo_core.v",
fw_path + "/sram_fifo/sram_fifo.v",
os.path.dirname(__file__) + "/../firmware/src/sram_test.v",
os.path.dirname(__file__) + "/../tests/tb.v",
],
top_level="tb",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
class TestExampleMIO(unittest.TestCase):
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(os.path.dirname(__file__), '../src/example.v')],
top_level='example',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def test_gpio(self):
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0], ret)
self.chip['GPIO_LED']['LED'] = 0x01
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x21], ret)
self.chip['GPIO_LED']['LED'] = 0x02
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x42], ret)
self.chip['GPIO_LED']['LED'] = 0x03
self.chip['GPIO_LED'].write()
ret = self.chip['GPIO_LED'].get_data()
self.assertEqual([0x63], ret)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def setUp(self):
cocotb_compile_and_run([
os.path.join(os.path.dirname(__file__), 'jtag_tap.v'),
os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v')]
)
self.chip = Dut(cnfg_yaml)
self.chip.init(init_yaml)
class TestSimTlu(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run(['test_SimTlu.v'])
cnfg = yaml.load(cnfg_yaml)
self.chip = Dut(cnfg)
self.chip.init()
def test_version(self):
self.assertEqual(self.chip['tlu'].VERSION, 1)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
time.sleep(1)
subprocess.call('make clean', shell=True)
subprocess.call('rm -f Makefile', shell=True)
class Silab_relay(object):
def __init__(self, yaml='relay.yaml'):
self.dut = Dut(yaml)
self.dut.init()
time.sleep(1)
def switch(self, channel, state='toggle'):
'''
Sets one channel of relay card to defined state or toggles
'''
if channel == 'All' or channel == 'all' or channel == 99:
send_channel = 99
elif type(channel) == int and channel >= 0 and channel <= 9:
send_channel = channel + 2
else:
raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')
if state == 'On' or state == 'on' or state == 1 or state == True:
send_state = 1
elif state == 'Off' or state == 'off' or state == 0 or state == False:
send_state = 0
elif state == 'toggle' or state == 'Toggle':
send_state = 0 if bool(self.get_state(channel)) else 1
print send_state
raise NotImplementedError
else:
raise ValueError('State has to be either 1/0 or \'On\'/\'Off\' or True/False.')
self.dut['Arduino'].set_output(channel=send_channel, value=send_state)
def switch_to(self, channel):
self.switch('all', 'off')
self.switch(channel, 'on')
def get_state(self, channel='all'):
'''
Will only work as long as connection is open. On reconnect, the arduino resets and sets all pins to LOW.
'''
state = self.dut['Arduino'].get_state()
if channel == 'all' or channel == 'All' or channel == 99:
return state
elif type(channel) == int and channel >= 0 and channel <= 9:
return state[channel]
else:
raise ValueError('Channel has to be integer between 0 and 9 or String \'All\'.')
class TestSimGpio(unittest.TestCase):
def __init__(self, testname, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
super(TestSimGpio, self).__init__(testname)
self._test_tb = tb
self._sim_bus = bus_drv
self._bus_split_def = ()
if bus_split is not False:
if bus_split == 'sbus':
self._bus_split_def = ("BASIL_SBUS",)
elif bus_split == 'top':
self._bus_split_def = ("BASIL_TOPSBUS",)
def setUp(self):
cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
self.chip['GPIO'].set_output_en([0xff, 0, 0]) # to remove 'z in simulation
ret = self.chip['GPIO'].get_data()
self.assertEqual([0, 0, 0], ret)
self.chip['GPIO'].set_output_en([0x0f, 0, 0])
self.chip['GPIO'].set_data([0xe3, 0xfa, 0x5a])
ret = self.chip['GPIO'].get_data()
self.assertEqual([0x33, 0x5a, 0x5a], ret)
ret = self.chip['GPIO2'].get_data()
self.assertEqual([0xa5, 0xcd], ret)
def test_io_register(self):
self.chip['GPIO'].set_output_en([0xff, 0, 0]) # to remove 'z in simulation
self.chip['GPIO']['OUT'] = 0xa5
self.chip['GPIO'].write()
ret = self.chip['GPIO'].get_data()
self.assertEqual([0, 0xa5, 0xa5], ret)
# TODO: Add register readback and comparison
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
class TestSimGpio(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimAdcRx.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
pattern = [1, 0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7]
self.chip['SEQ_GEN'].set_data(pattern)
self.chip['PULSE_GEN'].set_delay(1)
self.chip['PULSE_GEN'].set_width(1)
self.chip['SEQ_GEN'].set_en_ext_start(True)
self.chip['SEQ_GEN'].set_size(8)
self.chip['SEQ_GEN'].set_repeat(1)
# this is to have something in memory and not X
self.chip['PULSE_GEN'].start()
self.chip['SEQ_GEN'].is_done()
self.chip['SEQ_GEN'].is_done()
while(not self.chip['SEQ_GEN'].is_done()):
pass
# take some data
self.chip['FADC'].set_align_to_sync(True)
self.chip['FADC'].set_data_count(16)
self.chip['FADC'].set_single_data(True)
self.chip['FADC'].start()
self.chip['PULSE_GEN'].start()
self.chip['SEQ_GEN'].is_done()
self.chip['SEQ_GEN'].is_done()
while(not self.chip['FADC'].is_done()):
pass
ret = self.chip['fifo'].get_data()
self.assertEqual(ret[2:2 + 8].tolist(), [0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107])
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def __init__(self,
conf_file="../examples/cooling.yaml",
setpoint=-20,
monitor=False):
# Setup logging
self.log = logging.getLogger('N2 Cooling')
fh = logging.FileHandler('cooling_2021-05-12_2e15.log')
fh.setLevel(logging.INFO)
fh.setFormatter(logging.Formatter(FORMAT))
self.log.addHandler(fh)
# Setup online monitor
if monitor:
try:
context = zmq.Context()
self.socket = context.socket(zmq.PUB)
self.socket.bind(monitor)
self.log.info("Sending data to server %s" % monitor)
except zmq.error.ZMQError:
self.log.warning("Cannot connect to socket for data sending")
self.socket = None
else:
self.socket = None
# Set up temperature log file
self.temp_type = np.dtype([('timestamp', 'u4'), ('temp_1', 'f4'),
('temp_2', 'f4'), ('humidity_1', 'f4'),
('humidity_2', 'f4')])
self.output_file = tb.open_file('cooling.h5', 'a')
if '/temperature' in self.output_file: # Table already exists
self.temp_table = self.output_file.root.temperature
else:
self.temp_table = self.output_file.create_table(
self.output_file.root,
name='temperature',
description=self.temp_type,
filters=tb.Filters(complevel=5, complib='blosc'))
self.setpoint = setpoint
devices = Dut(conf_file)
devices.init()
self.temp_sensors = devices["sensirion"]
self.valve = devices["bronkhorst"]
class TestSimScpi(unittest.TestCase):
def setUp(self):
cfg = yaml.load(cnfg_yaml)
self.device = Dut(cfg)
self.device.init()
def test_read(self):
self.assertEqual(self.device['Pulser'].get_frequency(), u'100.00')
def test_write(self):
self.device['Pulser'].set_on()
self.assertEqual(self.device['Pulser'].get_on(), u'0')
def test_exception(self):
with self.assertRaises(ValueError):
self.device['Pulser'].unknown_function()
def tearDown(self):
self.device.close()
class TestSimScpi(unittest.TestCase):
def setUp(self):
cfg = yaml.load(cnfg_yaml)
self.device = Dut(cfg)
self.device.init()
def test_read(self):
self.assertEqual(self.device['Pulser'].get_frequency(), u'100.00')
def test_write(self):
self.device['Pulser'].set_on()
self.assertEqual(self.device['Pulser'].get_on(), u'0')
def test_exception(self):
with self.assertRaises(ValueError):
self.device['Pulser'].unknown_function()
def tearDown(self):
self.device.close()
def __init__(self,conf=""):
self.init_log()
if conf=="":
conf="ccpdlf.yaml"
self.dut=Dut(conf)
self.debug=0
self._build_img=np.vectorize(self._build_img_oneB)
self.tdac=np.zeros([24,114],int)
self.dut.init()
self.set_DACcurrent()
self.power()
def test_default(self):
self.cnfg['registers'][1]['fields'][0]['default'] = 0x01 # VINJECT
self.dut = Dut(self.cnfg)
self.dut.init()
mem = dict()
# mem[0] = 0 # reset
mem[0] = 1
mem[13] = 4
mem[16] = 0x08
mem[17] = 0
mem[18] = 0
self.dut['TEST2'].write()
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def test_default(self):
self.cnfg['registers'][1]['fields'][0]['default'] = 0x01 # VINJECT
self.dut = Dut(self.cnfg)
self.dut['spi_module']._require_version = "==1"
self.dut.init()
self.dut['spi_module']._mem_bytes = 32
mem = dict()
# mem[0] = 0 # reset
mem[0] = 1
mem[14] = 4
mem[16] = 0x08
mem[17] = 0
mem[18] = 0
self.dut['TEST2'].write()
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def setUp(self):
fw_path = os.path.join(get_basil_dir(), 'firmware/modules')
cocotb_compile_and_run([
os.path.join(fw_path, 'gpio/gpio.v'),
os.path.join(fw_path, 'utils/reset_gen.v'),
os.path.join(fw_path, 'utils/bus_to_ip.v'),
os.path.join(fw_path, 'utils/fx2_to_bus.v'),
os.path.join(os.path.dirname(__file__), '../src/example.v')],
top_level='example',
sim_bus='basil.utils.sim.SiLibUsbBusDriver'
)
with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg['transfer_layer'][0]['type'] = 'SiSim'
self.chip = Dut(cnfg)
self.chip.init()
def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/utils/fx2_to_bus.v",
os.path.dirname(__file__) + "/../src/example.v",
],
top_level="example",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/example.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
def scan(self, mask_steps=4, repeat_command=100, PrmpVbpDac=80, vthin2Dac=0, columns = [True] * 16, scan_range = [0, 0.2, 0.005], vthin1Dac = 80, preCompVbnDac = 50, mask_filename='', **kwargs):
'''Scan loop
Parameters
----------
mask : int
Number of mask steps.
repeat : int
Number of injections.
'''
inj_factor = 1.0
INJ_LO = 0.0
try:
dut = Dut(ScanBase.get_basil_dir(self)+'/examples/lab_devices/agilent33250a_pyserial.yaml')
dut.init()
logging.info('Connected to '+str(dut['Pulser'].get_info()))
except RuntimeError:
INJ_LO = 0.2
inj_factor = 2.0
logging.info('External injector not connected. Switch to internal one')
self.dut['INJ_LO'].set_voltage(INJ_LO, unit='V')
self.dut['global_conf']['PrmpVbpDac'] = 80
self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['vffDac'] = 24
self.dut['global_conf']['PrmpVbnFolDac'] = 51
self.dut['global_conf']['vbnLccDac'] = 1
self.dut['global_conf']['compVbnDac'] = 25
self.dut['global_conf']['preCompVbnDac'] = 50
self.dut.write_global()
self.dut['control']['RESET'] = 0b01
self.dut['control']['DISABLE_LD'] = 0
self.dut['control']['PIX_D_CONF'] = 0
self.dut['control'].write()
self.dut['control']['CLK_OUT_GATE'] = 1
self.dut['control']['CLK_BX_GATE'] = 1
self.dut['control'].write()
time.sleep(0.1)
self.dut['control']['RESET'] = 0b11
self.dut['control'].write()
self.dut['global_conf']['OneSr'] = 1
self.dut['global_conf']['TestHit'] = 0
self.dut['global_conf']['SignLd'] = 0
self.dut['global_conf']['InjEnLd'] = 0
self.dut['global_conf']['TDacLd'] = 0
self.dut['global_conf']['PixConfLd'] = 0
self.dut.write_global()
#self.dut['global_conf']['OneSr'] = 0 #all multi columns in parallel
self.dut['global_conf']['ColEn'][:] = bitarray.bitarray([True] * 16) #(columns)
self.dut['global_conf']['ColSrEn'][:] = bitarray.bitarray([True] * 16)
self.dut.write_global()
self.dut['pixel_conf'].setall(False)
self.dut.write_pixel()
self.dut['global_conf']['InjEnLd'] = 1
self.dut.write_global()
self.dut['global_conf']['InjEnLd'] = 0
mask_en = np.full([64,64], False, dtype = np.bool)
mask_tdac = np.full([64,64], 16, dtype = np.uint8)
for inx, col in enumerate(columns):
if col:
mask_en[inx*4:(inx+1)*4,:] = True
if mask_filename:
logging.info('Using pixel mask from file: %s', mask_filename)
with tb.open_file(mask_filename, 'r') as in_file_h5:
mask_tdac = in_file_h5.root.scan_results.tdac_mask[:]
mask_en = in_file_h5.root.scan_results.en_mask[:]
self.dut.write_en_mask(mask_en)
self.dut.write_tune_mask(mask_tdac)
self.dut['global_conf']['OneSr'] = 0
self.dut.write_global()
self.dut['inj'].set_delay(10000) #this seems to be working OK problem is probably bad injection on GPAC usually +0
self.dut['inj'].set_width(1000)
self.dut['inj'].set_repeat(repeat_command)
self.dut['inj'].set_en(False)
self.dut['trigger'].set_delay(400-4)
self.dut['trigger'].set_width(16)
self.dut['trigger'].set_repeat(1)
self.dut['trigger'].set_en(True)
###
self.dut['trigger'].set_delay(10000) #this seems to be working OK problem is probably bad injection on GPAC usually +0
self.dut['trigger'].set_width(16)
self.dut['trigger'].set_repeat(repeat_command)
self.dut['trigger'].set_en(False)
##
logging.debug('Configure TDC')
self.dut['tdc']['RESET'] = True
self.dut['tdc']['EN_TRIGGER_DIST'] = True
self.dut['tdc']['ENABLE_EXTERN'] = False
self.dut['tdc']['EN_ARMING'] = False
self.dut['tdc']['EN_INVERT_TRIGGER'] = False
self.dut['tdc']['EN_INVERT_TDC'] = False
self.dut['tdc']['EN_WRITE_TIMESTAMP'] = True
lmask = [1] + ( [0] * (mask_steps-1) )
lmask = lmask * ( (64 * 64) / mask_steps + 1 )
lmask = lmask[:64*64]
scan_range = np.arange(scan_range[0], scan_range[1], scan_range[2]) / inj_factor
for idx, k in enumerate(scan_range):
dut['Pulser'].set_voltage(INJ_LO, float(INJ_LO + k), unit='V')
self.dut['INJ_HI'].set_voltage( float(INJ_LO + k), unit='V')
time.sleep(0.5)
bv_mask = bitarray.bitarray(lmask)
with self.readout(scan_param_id = idx):
logging.info('Scan Parameter: %f (%d of %d)', k, idx+1, len(scan_range))
pbar = ProgressBar(maxval=mask_steps).start()
for i in range(mask_steps):
self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['preCompVbnDac'] = 50
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['PrmpVbpDac'] = 80
self.dut.write_global()
time.sleep(0.1)
self.dut['pixel_conf'][:] = bv_mask
self.dut.write_pixel_col()
self.dut['global_conf']['InjEnLd'] = 1
#self.dut['global_conf']['PixConfLd'] = 0b11
self.dut.write_global()
bv_mask[1:] = bv_mask[0:-1]
bv_mask[0] = 0
self.dut['global_conf']['vthin1Dac'] = vthin1Dac
self.dut['global_conf']['preCompVbnDac'] = preCompVbnDac
self.dut['global_conf']['vthin2Dac'] = vthin2Dac
self.dut['global_conf']['PrmpVbpDac'] = PrmpVbpDac
self.dut.write_global()
time.sleep(0.1)
#self.dut['inj'].start()
pbar.update(i)
while not self.dut['inj'].is_done():
pass
while not self.dut['trigger'].is_done():
pass
#self.dut['trigger'].set_repeat(0)
#self.dut['control']['CLK_BX_GATE'] = 0
#self.dut['control']['CLK_OUT_GATE'] = 0
#self.dut['control'].write()
print('!!!!!!!!!!!!!!!1')
self.dut['tdc'].ENABLE = True
self.dut['trigger'].start()
time.sleep(10)
self.dut['tdc'].ENABLE = False
print('!!!!!!!!!!!!!!!2')
#self.dut['control']['CLK_BX_GATE'] = 1
#self.dut['control']['CLK_OUT_GATE'] = 1
#self.dut['control'].write()
scan_results = self.h5_file.create_group("/", 'scan_results', 'Scan Masks')
self.h5_file.createCArray(scan_results, 'tdac_mask', obj=mask_tdac)
self.h5_file.createCArray(scan_results, 'en_mask', obj=mask_en)
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimSpi.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
class TestSimSpi(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimSpi.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
size = self.chip['spi'].get_size()
self.chip['gpio'].reset()
self.assertEqual(size, 16 * 8)
self.chip['spi'].set_data(range(16))
ret = self.chip['spi'].get_data(size=16, addr=0) # to read back what was written
self.assertEqual(ret.tolist(), range(16))
self.chip['spi'].set_data(range(16))
ret = self.chip['spi'].get_data(addr=0) # to read back what was written
self.assertEqual(ret.tolist(), range(16))
self.chip['spi'].start()
while(not self.chip['spi'].is_done()):
pass
ret = self.chip['spi'].get_data() # read back what was received (looped)
self.assertEqual(ret.tolist(), range(16))
# ext_start
self.chip['spi'].set_en(1)
self.assertEqual(self.chip['spi'].get_en(), 1)
self.chip['PULSE_GEN'].set_delay(1)
self.chip['PULSE_GEN'].set_width(1+size)
self.chip['PULSE_GEN'].set_repeat(1)
self.assertEqual(self.chip['PULSE_GEN'].get_delay(), 1)
self.assertEqual(self.chip['PULSE_GEN'].get_width(), 1+size)
self.assertEqual(self.chip['PULSE_GEN'].get_repeat(), 1)
self.chip['PULSE_GEN'].start()
while(not self.chip['PULSE_GEN'].is_done()):
pass
ret = self.chip['spi'].get_data() # read back what was received (looped)
self.assertEqual(ret.tolist(), range(16))
# spi_rx
ret = self.chip['spi_rx'].get_en()
self.assertEqual(ret, False)
self.chip['spi_rx'].set_en(True)
ret = self.chip['spi_rx'].get_en()
self.assertEqual(ret, True)
self.chip['spi'].start()
while(not self.chip['spi'].is_done()):
pass
ret = self.chip['fifo'].get_fifo_size()
self.assertEqual(ret, 32)
ret = self.chip['fifo'].get_data()
data0 = ret.astype(np.uint8)
data1 = np.right_shift(ret, 8).astype(np.uint8)
data = np.reshape(np.vstack((data1, data0)), -1, order='F')
self.assertEqual(data.tolist(), range(16))
def test_dut_iter(self):
conf = yaml.safe_load(cnfg_yaml)
def iter_conf():
for item in conf['registers']:
yield item
for item in conf['hw_drivers']:
yield item
for item in conf['transfer_layer']:
yield item
for mod, mcnf in zip(self.chip, iter_conf()):
self.assertEqual(mod.name, mcnf['name'])
self.assertEqual(mod.__class__.__name__, mcnf['type'])
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
value = int(get_voltage_reading(dev))
if (max_value > 0):
if max_value > value:
step = 1
else:
step = -1
else:
if max_value > value:
step = 1
else:
step = -1
while True:
value = int(get_voltage_reading(dev))
if value != max_value:
dev.set_voltage(value + step)
else:
break
if __name__ == "__main__":
dut = Dut('sourcemeter.yaml')
dut.init()
dut['Sourcemeter'].on()
#ramp_to(dut['Sourcemeter'], 15)
#ramp_down(dut['Sourcemeter'])
print status(dut['Sourcemeter'])
class TestSimSeq(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.getcwd() + '/test_SimSeq.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_io(self):
self.assertEqual(self.chip['SEQ_GEN'].get_mem_size(), 8 * 1024)
self.chip['SEQ']['S0'][0] = 1
self.chip['SEQ']['S1'][1] = 1
self.chip['SEQ']['S2'][2] = 1
self.chip['SEQ']['S3'][3] = 1
self.chip['SEQ']['S4'][12] = 1
self.chip['SEQ']['S5'][13] = 1
self.chip['SEQ']['S6'][14] = 1
self.chip['SEQ']['S7'][15] = 1
pattern = [0x01, 0x02, 0x04, 0x08, 0, 0, 0, 0, 0, 0, 0, 0, 0x10, 0x20, 0x40, 0x80]
self.chip['SEQ'].write(16)
ret = self.chip['SEQ'].get_data(size=16)
self.assertEqual(ret.tolist(), pattern)
rec_size = 16 * 4 + 8
self.chip['SEQ_REC'].set_en_ext_start(True)
self.chip['SEQ_REC'].set_size(rec_size)
self.chip['PULSE_GEN'].set_delay(1)
self.chip['PULSE_GEN'].set_width(1)
self.assertEqual(self.chip['PULSE_GEN'].get_delay(), 1)
self.assertEqual(self.chip['PULSE_GEN'].get_width(), 1)
self.chip['SEQ'].set_repeat(4)
self.chip['SEQ'].set_en_ext_start(True)
self.chip['SEQ'].set_size(16)
# self.chip['SEQ'].start()
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
self.assertEqual(ret.tolist(), [0x0] * 2 + pattern * 4 + [0x80] * 6) # 2 clk delay + pattern x4 + 6 x last pattern
#
self.chip['SEQ'].set_repeat_start(12)
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
self.assertEqual(ret.tolist(), [0x80] * 2 + pattern + pattern[12:] * 3 + [0x80] * 3 * 12 + [0x80] * 6) # 2 clk delay 0x80 > from last pattern + ...
self.chip['SEQ'].set_wait(4)
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
lpat = pattern[12:] + [0x80] * 4
self.assertEqual(ret.tolist(), [0x80] * 2 + pattern + [0x80] * 4 + lpat * 3 + [0x80] * (3 * 12 - 4 * 4) + [0x80] * 6)
#
rec_size = rec_size * 3
self.chip['SEQ_REC'].set_size(rec_size)
self.chip['SEQ'].set_clk_divide(3)
self.chip['SEQ'].set_wait(3)
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
lpat = pattern[12:] + [0x80] * 3
mu_pat = pattern + [0x80] * 3 + lpat * 3
fm = []
for i in mu_pat:
fm += [i, i, i]
self.assertEqual(ret.tolist(), [0x80] * 2 + fm + [0x80] * 94)
#
self.chip['SEQ'].set_wait(0)
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
lpat = pattern[12:]
mu_pat = pattern + lpat * 3
fm = []
for i in mu_pat:
fm += [i, i, i]
self.assertEqual(ret.tolist(), [0x80] * 2 + fm + [0x80] * (94 + 4 * 3 * 3))
# nested loop test
pattern = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
self.chip['SEQ'].set_data(pattern)
self.chip['SEQ'].set_repeat(4)
self.chip['SEQ'].set_repeat_start(2)
self.chip['SEQ'].set_nested_start(8)
self.chip['SEQ'].set_nested_stop(12)
self.chip['SEQ'].set_nested_repeat(3)
self.chip['SEQ'].set_clk_divide(1)
self.chip['PULSE_GEN'].start()
while(not self.chip['SEQ'].is_done()):
pass
exp_pattern = [0x10, 0x10]
exp_pattern += pattern[0:2]
rep = pattern[2:8]
rep += pattern[8:12] * 3
rep += pattern[12:16]
exp_pattern += rep * 4
exp_pattern += [16] * 124
ret = self.chip['SEQ_REC'].get_data(size=rec_size)
self.assertEqual(ret.tolist(), exp_pattern)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def __init__(self, config='qmca.yaml', sample_count=200, sample_delay=50, threshold=2000, channel=0, adc_differential_voltage=1.9, socket_addr='tcp://127.0.0.1:5678', write_after_n_events = 100000):
'''
Parameters
----------
sample_count : int
Length of event in ADC samples
sample_delay : int
Number of ADC samples to add to event before detected peak
threshold : int [0:2**14]
ADC threshold
channel : int [0:3]
qMCA channel number
outfile_name : string
Filename of the raw data output file
socket_addr : string
Socket address of Online Monitor
'''
self.event_count = 0
self.count_lost = 0
self.main_thread = None
self.exit = threading.Event()
self.write_after_n_events = write_after_n_events
self.sample_count = sample_count
self.sample_delay = sample_delay
# Setup ZeroMQ socket
self.socket = zmq.Context().socket(zmq.PUSH)
self.socket.setsockopt(zmq.SNDHWM, 10)
self.socket.setsockopt(zmq.LINGER, 500)
self.socket.bind(socket_addr)
# Setup Dut
self.dut = Dut(config)
self.dut.init()
self.dut['PWR0'].set_current_limit(100, unit='mA')
self.dut['PWR0'].set_voltage(1.8, unit='V')
self.dut['PWR0'].set_enable(True)
self.dut['PWR1'].set_current_limit(100, unit='mA')
self.dut['PWR1'].set_voltage(1.8, unit='V')
self.dut['PWR1'].set_enable(True)
self.dut['PWR2'].set_current_limit(100, unit='mA')
self.dut['PWR2'].set_voltage(1.8, unit='V')
self.dut['PWR2'].set_enable(True)
self.dut['PWR3'].set_current_limit(100, unit='mA')
self.dut['PWR3'].set_voltage(1.8, unit='V')
self.dut['PWR3'].set_enable(True)
# Reset ADC and SRAM
self.dut['fadc0_rx'].reset()
self.dut['DATA_FIFO'].reset()
self.adc_differential_voltage = adc_differential_voltage
self.set_adc_differential_voltage(adc_differential_voltage)
self.set_adc_eventsize(self.sample_count, self.sample_delay)
self.set_threshold(threshold)
self.select_channel(channel)
def scan(self, pix_list=((6, 20),), mask_steps=4, repeat_command=101, columns=[True] * 16, scan_range=[0, 1.2, 0.1],
vthin1Dac=80, vthin2Dac=0, PrmpVbpDac=80, preCompVbnDac=50, mask_filename='', **kwargs):
'''Scan loop
This scan is to measure time walk. The charge injection can be driven by the GPAC or an external device.
In the latter case the device is Agilent 33250a connected through serial port.
The time walk and TOT are measured by a TDC module in the FPGA.
The output is an .h5 file (data) and an .html file with plots.
Parameters
----------
mask : int
Number of mask steps.
repeat : int
Number of injections.
'''
inj_factor = 1.0
INJ_LO = 0.0
try:
dut = Dut(ScanBase.get_basil_dir(self) + '/examples/lab_devices/agilent33250a_pyserial.yaml')
dut.init()
logging.info('Connected to ' + str(dut['Pulser'].get_info()))
except RuntimeError:
INJ_LO = 0.2
inj_factor = 2.0
logging.info('External injector not connected. Switch to internal one')
self.dut['INJ_LO'].set_voltage(INJ_LO, unit='V')
self.dut['global_conf']['PrmpVbpDac'] = 80
# self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['vffDac'] = 24
self.dut['global_conf']['PrmpVbnFolDac'] = 51
self.dut['global_conf']['vbnLccDac'] = 1
self.dut['global_conf']['compVbnDac'] = 25
self.dut['global_conf']['preCompVbnDac'] = 110 # 50
self.dut.write_global()
self.dut['control']['RESET'] = 0b01
self.dut['control']['DISABLE_LD'] = 0
self.dut['control']['PIX_D_CONF'] = 0
self.dut['control'].write()
self.dut['control']['CLK_OUT_GATE'] = 1
self.dut['control']['CLK_BX_GATE'] = 1
self.dut['control'].write()
time.sleep(0.1)
self.dut['control']['RESET'] = 0b11
self.dut['control'].write()
self.dut['global_conf']['OneSr'] = 1
self.dut['global_conf']['TestHit'] = 0
self.dut['global_conf']['SignLd'] = 0
self.dut['global_conf']['InjEnLd'] = 0
self.dut['global_conf']['TDacLd'] = 0
self.dut['global_conf']['PixConfLd'] = 0
self.dut.write_global()
self.dut['global_conf']['ColEn'][:] = bitarray.bitarray([True] * 16) # (columns)
self.dut['global_conf']['ColSrEn'][:] = bitarray.bitarray([True] * 16)
self.dut.write_global()
self.dut['pixel_conf'].setall(False)
self.dut.write_pixel()
self.dut['global_conf']['InjEnLd'] = 1
self.dut.write_global()
self.dut['global_conf']['InjEnLd'] = 0
mask_en = np.full([64, 64], False, dtype=np.bool)
mask_tdac = np.full([64, 64], 16, dtype=np.uint8)
for inx, col in enumerate(columns):
if col:
mask_en[inx * 4:(inx + 1) * 4, :] = True
if mask_filename:
logging.info('Using pixel mask from file: %s', mask_filename)
with tb.open_file(mask_filename, 'r') as in_file_h5:
mask_tdac = in_file_h5.root.scan_results.tdac_mask[:]
mask_en = in_file_h5.root.scan_results.en_mask[:]
self.dut.write_en_mask(mask_en)
self.dut.write_tune_mask(mask_tdac)
self.dut['global_conf']['OneSr'] = 1
self.dut.write_global()
self.dut['inj'].set_delay(50000) # 1 zero more
self.dut['inj'].set_width(1000)
self.dut['inj'].set_repeat(repeat_command)
self.dut['inj'].set_en(False)
self.dut['trigger'].set_delay(400 - 4)
self.dut['trigger'].set_width(16)
self.dut['trigger'].set_repeat(1)
self.dut['trigger'].set_en(False)
logging.debug('Enable TDC')
self.dut['tdc']['RESET'] = True
self.dut['tdc']['EN_TRIGGER_DIST'] = True
self.dut['tdc']['ENABLE_EXTERN'] = False
self.dut['tdc']['EN_ARMING'] = False
self.dut['tdc']['EN_INVERT_TRIGGER'] = False
self.dut['tdc']['EN_INVERT_TDC'] = False
self.dut['tdc']['EN_WRITE_TIMESTAMP'] = True
scan_range = np.arange(scan_range[0], scan_range[1], scan_range[2]) / inj_factor
scan_range = np.append(scan_range, 0.3 / inj_factor)
scan_range = np.append(scan_range, 0.6 / inj_factor)
scan_range = np.append(scan_range, 1.0 / inj_factor)
self.pixel_list = pix_list
p_counter = 0
for pix in pix_list:
mask_en = np.full([64, 64], False, dtype=np.bool)
mask_en[pix[0], pix[1]] = True
self.dut.write_en_mask(mask_en)
self.dut.write_inj_mask(mask_en)
self.inj_charge = []
for idx, k in enumerate(scan_range):
dut['Pulser'].set_voltage(INJ_LO, float(INJ_LO + k), unit='V')
self.dut['INJ_HI'].set_voltage(float(INJ_LO + k), unit='V')
self.inj_charge.append(float(k) * 1000.0 * analysis.cap_fac())
time.sleep(0.5)
with self.readout(scan_param_id=idx + p_counter * len(scan_range)):
logging.info('Scan Parameter: %f (%d of %d)', k, idx + 1, len(scan_range))
self.dut['tdc']['ENABLE'] = True
self.dut['global_conf']['vthin1Dac'] = 255
self.dut['global_conf']['vthin2Dac'] = 0
self.dut['global_conf']['PrmpVbpDac'] = 80
self.dut['global_conf']['preCompVbnDac'] = 50
self.dut.write_global()
time.sleep(0.1)
self.dut['global_conf']['vthin1Dac'] = vthin1Dac
self.dut['global_conf']['vthin2Dac'] = vthin2Dac
self.dut['global_conf']['PrmpVbpDac'] = PrmpVbpDac
self.dut['global_conf']['preCompVbnDac'] = preCompVbnDac
self.dut.write_global()
time.sleep(0.1)
self.dut['inj'].start()
while not self.dut['inj'].is_done():
pass
while not self.dut['trigger'].is_done():
pass
self.dut['tdc'].ENABLE = 0
p_counter += 1
def setUp(self):
cocotb_compile_and_run([os.path.dirname(__file__) + '/test_SimI2c.v'])
self.chip = Dut(cnfg_yaml)
self.chip.init()
class qmca(object):
'''Sets up qMCA setup. Reads data via USB from qMCA setup and sends it via ZeroMQ to Online Monitor.
8000 Hz of waveforms with 200 samples can be read out'''
def __init__(self, config='qmca.yaml', sample_count=200, sample_delay=50, threshold=2000, channel=0, adc_differential_voltage=1.9, socket_addr='tcp://127.0.0.1:5678', write_after_n_events = 100000):
'''
Parameters
----------
sample_count : int
Length of event in ADC samples
sample_delay : int
Number of ADC samples to add to event before detected peak
threshold : int [0:2**14]
ADC threshold
channel : int [0:3]
qMCA channel number
outfile_name : string
Filename of the raw data output file
socket_addr : string
Socket address of Online Monitor
'''
self.event_count = 0
self.count_lost = 0
self.main_thread = None
self.exit = threading.Event()
self.write_after_n_events = write_after_n_events
self.sample_count = sample_count
self.sample_delay = sample_delay
# Setup ZeroMQ socket
self.socket = zmq.Context().socket(zmq.PUSH)
self.socket.setsockopt(zmq.SNDHWM, 10)
self.socket.setsockopt(zmq.LINGER, 500)
self.socket.bind(socket_addr)
# Setup Dut
self.dut = Dut(config)
self.dut.init()
self.dut['PWR0'].set_current_limit(100, unit='mA')
self.dut['PWR0'].set_voltage(1.8, unit='V')
self.dut['PWR0'].set_enable(True)
self.dut['PWR1'].set_current_limit(100, unit='mA')
self.dut['PWR1'].set_voltage(1.8, unit='V')
self.dut['PWR1'].set_enable(True)
self.dut['PWR2'].set_current_limit(100, unit='mA')
self.dut['PWR2'].set_voltage(1.8, unit='V')
self.dut['PWR2'].set_enable(True)
self.dut['PWR3'].set_current_limit(100, unit='mA')
self.dut['PWR3'].set_voltage(1.8, unit='V')
self.dut['PWR3'].set_enable(True)
# Reset ADC and SRAM
self.dut['fadc0_rx'].reset()
self.dut['DATA_FIFO'].reset()
self.adc_differential_voltage = adc_differential_voltage
self.set_adc_differential_voltage(adc_differential_voltage)
self.set_adc_eventsize(self.sample_count, self.sample_delay)
self.set_threshold(threshold)
self.select_channel(channel)
def start(self, out_filename='event_data'):
self.out_filename = out_filename + '.h5'
logging.info('Starting main loop in new thread.')
self.main_thread = threading.Thread(target=self._main_loop)
self.main_thread.start()
def stop(self):
self.exit.set()
if self.main_thread:
self.main_thread.join(timeout=1)
self.main_thread = None
logging.info('Measurement stopped. Recorded %i events.' % self.event_count)
else:
logging.info('No measurement was running.')
def reset_dut(self):
self.dut['fadc0_rx'].reset()
self.dut['DATA_FIFO'].reset()
self.set_adc_differential_voltage(self.adc_differential_voltage)
self.set_adc_eventsize(self.sample_count, self.sample_delay)
self.event_count = 0
self.count_lost = 0
self.main_thread = None
def set_threshold(self, threshold):
self.dut['TH']['TH'] = int(threshold)
self.dut['TH'].write()
self.threshold = threshold
def select_channel(self, channel):
self.dut['TH']['SEL_ADC_CH'] = channel
self.dut['TH'].write()
self.channel = channel
def set_adc_differential_voltage(self, value):
self.adc_differential_voltage = value
self.dut['VSRC3'].set_voltage(value, unit='V')
def set_adc_eventsize(self, sample_count, sample_delay):
self.dut['fadc0_rx'].set_delay(sample_delay)
self.dut['fadc0_rx'].set_data_count(sample_count)
self.dut['fadc0_rx'].set_single_data(True)
self.dut['fadc0_rx'].set_en_trigger(True)
self.sample_count = sample_count
self.sample_delay = sample_delay
def _send_data(self, data, name='qMCA'):
try:
data_meta_data = dict(
name=name,
dtype=str(data.dtype),
shape=data.shape,
thr = self.threshold,
ch = self.channel
)
self.socket.send_json(data_meta_data, flags=zmq.SNDMORE | zmq.NOBLOCK)
self.socket.send(data, flags=zmq.NOBLOCK) # PyZMQ supports sending numpy arrays without copying any data
except zmq.Again:
pass
def _record_data(self):
'''
Reads raw event data from SRAM and splits data stream into events
----------
Returns:
event_data : np.ndarray
Numpy array of single event numpy arrays
'''
self.count_lost = self.dut['fadc0_rx'].get_count_lost()
# print 'count_lost is %d' % self.count_lost
# print 'event_count is %d' % self.event_count
if self.count_lost > 0:
logging.error('SRAM FIFO overflow number %d. Skip data.', self.count_lost)
self.dut['fadc0_rx'].reset()
self.set_adc_eventsize(self.sample_count, self.sample_delay)
#return
single_data = self.dut['DATA_FIFO'].get_data() # Read raw data from SRAM
try:
if single_data.shape[0] > 200:
selection = np.where(single_data & 0x10000000 == 0x10000000)[0] # Make mask from new-event-bit
event_data = np.bitwise_and(single_data, 0x00003fff).astype(np.uint32) # Remove new-event-bit from data
event_data = np.split(event_data, selection) # Split data into events by means of mask
event_data = event_data[1:-1] # Remove first and last event in case of chopping
event_data = np.vstack(event_data) # Stack events together
else:
event_data = np.asarray([np.bitwise_and(single_data, 0x00003fff).astype(np.uint32)])
if event_data.shape[1] == self.sample_count:
return event_data
except ValueError as e:
logging.error('_record_data() experienced a ValueError: ' + str(e))
return
def _main_loop(self):
logging.info('Beginning measurement. Please open Online Monitor.')
last_mod_value = 0
with tb.open_file(self.out_filename, 'w') as self.output_file:
output_array = self.output_file.createEArray(self.output_file.root, name='event_data', atom=tb.UIntAtom(), shape=(0, self.sample_count), title='The raw events from the ADC', filters=tb.Filters(complib='blosc', complevel=5, fletcher32=False))
while not self.exit.wait(0.01):
events_data = self._record_data()
if np.any(events_data):
self._send_data(events_data)
try:
output_array.append(events_data)
except ValueError:
print events_data, events_data.shape
self.event_count += events_data.shape[0]
if (self.event_count % self.write_after_n_events < last_mod_value):
logging.info('Recorded %d events. Write data to disk.', self.write_after_n_events)
output_array.flush()
last_mod_value = self.event_count % self.write_after_n_events
output_array.flush()
def setUp(self):
cfg = yaml.load(cnfg_yaml)
self.device = Dut(cfg)
self.device.init()
class TestClass(unittest.TestCase):
@classmethod
def setUpClass(cls):
cls.cnfg = yaml.load(cnfg_yaml)
cls.dut = Dut(cls.cnfg)
cls.dut['spi_module']._require_version = "==1"
cls.dut.init()
cls.dut['spi_module']._mem_bytes = 4
def test_mem_bytes(self):
self.dut.init()
self.dut['spi_module']._mem_bytes = 4
self.assertEqual(4, self.dut['spi_module'].MEM_BYTES)
self.assertRaises(ValueError, self.dut['spi_module'].set_data, [1, 2, 3, 4, 5])
def test_init_simple(self):
self.dut['TEST1'].write()
mem = dict()
# mem[0] = 0 # reset
# mem[0] = 1
mem[16] = 0 # has an offset of 16 bytes
mem[17] = 0
mem[18] = 0
mem[19] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'][0] = 1
self.dut['TEST1'].write()
mem[19] = 1
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'][31] = 1
self.dut['TEST1'].write()
mem[16] = 0x80
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'] = 0
self.dut['TEST1'].write()
mem[16] = 0
mem[19] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'] = 0xa55a8001
self.dut['TEST1'].write()
mem[16] = 0xa5
mem[17] = 0x5a
mem[18] = 0x80
mem[19] = 0x01
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'] = 0
self.dut['TEST1'][11:4] = 0xff
self.dut['TEST1'].write()
mem[16] = 0x0
mem[17] = 0x0
mem[18] = 0x0f
mem[19] = 0xf0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'] = 0
self.dut['TEST1'][11:4] = '10000001'
self.dut['TEST1'].write()
mem[16] = 0x0
mem[17] = 0x0
mem[18] = 0x08
mem[19] = 0x10
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST1'] = 0
self.dut['TEST1'][11:4] = bitarray('00011000')
self.dut['TEST1'].write()
mem[16] = 0x0
mem[17] = 0x0
mem[18] = 0x01
mem[19] = 0x80
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def test_bit_order(self):
self.dut['TEST2'].write()
mem = dict()
# mem[0] = 0 # reset
mem[0] = 1
mem[14] = 4
mem[16] = 0
mem[17] = 0
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VINJECT'] = 0x01
self.dut['TEST2'].write()
mem[16] = 0x08
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VINJECT'] = 0x02
self.dut['TEST2'].write()
mem[16] = 0x10
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VINJECT'] = 0x04
self.dut['TEST2'].write()
mem[16] = 0x04
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VINJECT'] = 0x08
self.dut['TEST2'].write()
mem[16] = 0x20
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VINJECT'] = 0
self.dut['TEST2']['VINJECT'][0] = 1
self.dut['TEST2'].write()
mem[16] = 0x04
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def test_repeat(self):
self.dut['dummy_tl'].mem = dict()
# self.dut['TEST2'] = 0
self.dut['TEST2']['VINJECT'] = 0
self.dut['TEST2']['VPULSE'] = 0
self.dut['TEST2'].write()
mem = dict()
# mem[0] = 1
mem[16] = 0
mem[17] = 0
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['COLUMN'][0]['EnR'] = 1
self.dut['TEST2'].write()
mem[17] = 0x02
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['COLUMN'][1]['DACR'] = 1
self.dut['TEST2'].write()
mem[18] = 0x10
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def test_default(self):
self.cnfg['registers'][1]['fields'][0]['default'] = 0x01 # VINJECT
self.dut = Dut(self.cnfg)
self.dut['spi_module']._require_version = "==1"
self.dut.init()
self.dut['spi_module']._mem_bytes = 32
mem = dict()
# mem[0] = 0 # reset
mem[0] = 1
mem[14] = 4
mem[16] = 0x08
mem[17] = 0
mem[18] = 0
self.dut['TEST2'].write()
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
def test_fields(self):
self.dut['dummy_tl'].mem = dict()
self.dut['TEST2']['VINJECT'] = 0
self.dut['TEST2']['VPULSE'] = 0
self.dut['TEST2'].write()
mem = dict()
# mem[0] = 1
mem[16] = 0
mem[17] = 0
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VPULSE'] = 0x5
self.dut['TEST2'].write()
mem = dict()
mem[16] = 0
mem[17] = 0x50
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VPULSE'] = bitarray('100001')
self.dut['TEST2'].write()
mem = dict()
mem[16] = 0x02
mem[17] = 0x10
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VPULSE'] = '100001'
self.dut['TEST2'].write()
mem = dict()
mem[16] = 0x02
mem[17] = 0x10
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
self.dut['TEST2']['VPULSE'] = 0b100011
self.dut['TEST2'].write()
mem = dict()
mem[16] = 0x02
mem[17] = 0x30
mem[18] = 0
self.assertDictEqual(mem, self.dut['dummy_tl'].mem)
class TestSimTlu(unittest.TestCase):
def setUp(self):
cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimTlu.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
def test_simple_trigger_veto(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_MODE = 0
self.chip['tlu'].TRIGGER_SELECT = 2
self.chip['tlu'].TRIGGER_VETO_SELECT = 2
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x07]) # trigger + veto
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 1)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 1)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000 + 0)
def test_simple_trigger_veto_disabled(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_MODE = 0
self.chip['tlu'].TRIGGER_SELECT = 2
self.chip['tlu'].TRIGGER_VETO_SELECT = 252
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x01]) # issue a second time, wait for reset
self.chip['gpio'].set_data([0x07]) # trigger + veto
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 2)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 2)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000 + 0)
self.assertEqual(data[1], 0x80000000 + 1)
def test_simple_trigger_threshold(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_MODE = 0
self.chip['tlu'].TRIGGER_SELECT = 4 # select single pulse trigger
self.chip['tlu'].TRIGGER_THRESHOLD = 1 # at least two clock cycles
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x01]) # issue a second time, wait for reset
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 2)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 2)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000 + 0)
self.assertEqual(data[1], 0x80000000 + 1)
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_THRESHOLD = 2 # at least two clock cycles
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 0)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 0)
def test_simple_trigger_max_triggers(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].MAX_TRIGGERS = 2
self.chip['tlu'].TRIGGER_MODE = 0
self.chip['tlu'].TRIGGER_SELECT = 2
self.chip['tlu'].TRIGGER_VETO_SELECT = 252
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
self.chip['gpio'].set_data([0x03]) # trigger
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 2)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 2)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000 + 0)
self.assertEqual(data[1], 0x80000000 + 1)
def test_simple_trigger(self):
self.chip['tlu'].TRIGGER_COUNTER = 10
self.chip['tlu'].TRIGGER_MODE = 0
self.chip['tlu'].TRIGGER_SELECT = 1
self.chip['tlu'].TRIGGER_VETO_SELECT = 0
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
readings = 0
while(self.chip['sram'].get_fifo_int_size() < 4 and readings < 1000):
readings += 1
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertGreaterEqual(self.chip['sram'].get_fifo_int_size(), 4)
self.assertGreaterEqual(self.chip['tlu'].TRIGGER_COUNTER, 14)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000 + 10)
self.assertEqual(data[1], 0x80000000 + 11)
self.assertEqual(data[2], 0x80000000 + 12)
self.assertEqual(data[3], 0x80000000 + 13)
def test_tlu_trigger_handshake(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_MODE = 3
self.chip['tlu'].TRIGGER_VETO_SELECT = 255
self.chip['tlu'].EN_TLU_VETO = 0
# self.chip['tlu'].DATA_FORMAT = 2
# self.chip['tlu'].TRIGGER_LOW_TIMEOUT = 5
# self.chip['tlu'].TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES = 0
# self.chip['tlu'].HANDSHAKE_BUSY_VETO_WAIT_CYCLES = 0
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01])
readings = 0
while(self.chip['sram'].get_fifo_int_size() < 4 and readings < 1000):
readings += 1
# self.chip['CONTROL']['ENABLE'] = 0
self.chip['gpio'].set_data([0x00])
self.assertGreaterEqual(self.chip['sram'].get_fifo_int_size(), 4)
self.assertGreaterEqual(self.chip['tlu'].TRIGGER_COUNTER, 4)
self.assertGreaterEqual(self.chip['tlu'].CURRENT_TLU_TRIGGER_NUMBER, 3)
data = self.chip['sram'].get_data()
self.assertEqual(data[0], 0x80000000)
self.assertEqual(data[1], 0x80000001)
self.assertEqual(data[2], 0x80000002)
self.assertEqual(data[3], 0x80000003)
def test_tlu_trigger_handshake_veto(self):
self.chip['tlu'].TRIGGER_COUNTER = 0
self.chip['tlu'].TRIGGER_MODE = 3
self.chip['tlu'].TRIGGER_VETO_SELECT = 1
self.chip['tlu'].EN_TLU_VETO = 1
# self.chip['CONTROL']['ENABLE'] = 1
self.chip['gpio'].set_data([0x01]) # ext enable trigger/TLU
readings = 0
while(self.chip['sram'].get_fifo_int_size() == 0 and readings < 1000):
readings += 1
self.assertEqual(self.chip['sram'].get_fifo_int_size(), 0)
self.assertEqual(self.chip['tlu'].TRIGGER_COUNTER, 0)
self.assertEqual(self.chip['tlu'].CURRENT_TLU_TRIGGER_NUMBER, 0)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
def setUp(self):
cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimTlu.v')])
self.chip = Dut(cnfg_yaml)
self.chip.init()
class TestSram(unittest.TestCase):
def setUp(self):
fw_path = get_basil_dir() + "/firmware/modules"
cocotb_compile_and_run(
[
fw_path + "/gpio/gpio.v",
fw_path + "/utils/reset_gen.v",
fw_path + "/utils/bus_to_ip.v",
fw_path + "/rrp_arbiter/rrp_arbiter.v",
fw_path + "/utils/ODDR_sim.v",
fw_path + "/utils/generic_fifo.v",
fw_path + "/utils/cdc_pulse_sync.v",
fw_path + "/utils/fx2_to_bus.v",
fw_path + "/pulse_gen/pulse_gen.v",
fw_path + "/pulse_gen/pulse_gen_core.v",
fw_path + "/sram_fifo/sram_fifo_core.v",
fw_path + "/sram_fifo/sram_fifo.v",
os.path.dirname(__file__) + "/../firmware/src/sram_test.v",
os.path.dirname(__file__) + "/../tests/tb.v",
],
top_level="tb",
sim_bus="basil.utils.sim.SiLibUsbBusDriver",
)
with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f:
cnfg = yaml.load(f)
# change to simulation interface
cnfg["transfer_layer"][0]["type"] = "SiSim"
self.chip = Dut(cnfg)
self.chip.init()
def test_simple(self):
self.chip["CONTROL"]["COUNTER_EN"] = 1
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
self.chip["CONTROL"]["COUNTER_EN"] = 0
self.chip["CONTROL"].write()
for _ in range(10):
self.chip["CONTROL"].write()
ret = self.chip["fifo"].get_data()
self.chip["CONTROL"]["COUNTER_EN"] = 1
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
self.chip["CONTROL"]["COUNTER_EN"] = 0
for _ in range(10):
self.chip["CONTROL"].write()
ret = np.hstack((ret, self.chip["fifo"].get_data()))
x = np.arange(175 * 4, dtype=np.uint8)
x.dtype = np.uint32
self.assertTrue(np.alltrue(ret == x))
self.chip["fifo"].reset()
self.chip["CONTROL"]["COUNTER_EN"] = 1
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
self.chip["CONTROL"]["COUNTER_EN"] = 0
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
self.chip["CONTROL"].write()
ret = np.hstack((ret, self.chip["fifo"].get_data()))
x = np.arange(245 * 4, dtype=np.uint8)
x.dtype = np.uint32
self.assertEqual(ret.tolist(), x.tolist())
def test_full(self):
self.chip["CONTROL"]["COUNTER_EN"] = 1
self.chip["CONTROL"].write()
for _ in range(2):
self.chip["fifo"].get_fifo_size()
self.chip["CONTROL"]["COUNTER_EN"] = 0
self.chip["CONTROL"].write()
for _ in range(10):
self.chip["CONTROL"].write()
size = self.chip["fifo"].get_fifo_size()
self.assertEqual(size, 512)
ret = self.chip["fifo"].get_data()
ret = np.hstack((ret, self.chip["fifo"].get_data()))
x = np.arange(203 * 4, dtype=np.uint8)
x.dtype = np.uint32
self.assertTrue(np.alltrue(ret == x))
def test_overflow(self):
self.chip["CONTROL"]["COUNTER_EN"] = 1
self.chip["CONTROL"].write()
for _ in range(20):
self.chip["fifo"].get_fifo_size()
self.chip["CONTROL"]["COUNTER_EN"] = 0
self.chip["CONTROL"].write()
for _ in range(10):
self.chip["CONTROL"].write()
ret = self.chip["fifo"].get_data()
while self.chip["fifo"].get_fifo_size():
ret = np.hstack((ret, self.chip["fifo"].get_data()))
x = np.arange((128 + 1023) * 4, dtype=np.uint8)
x.dtype = np.uint32
self.assertTrue(np.alltrue(ret == x))
self.chip["pulse"].set_delay(1)
self.chip["pulse"].set_width(1)
self.chip["pulse"].start()
ret = self.chip["fifo"].get_data()
x = np.arange((128 + 1023) * 4, (128 + 1023 + 1) * 4, dtype=np.uint8)
x.dtype = np.uint32
self.assertEqual(ret, x)
def test_single(self):
self.chip["pulse"].set_delay(1)
self.chip["pulse"].set_width(1)
self.chip["pulse"].start()
self.assertEqual(self.chip["fifo"].get_data().tolist(), [0x03020100])
self.chip["pulse"].start()
self.assertEqual(self.chip["fifo"].get_data().tolist(), [0x07060504])
def test_pattern(self):
self.chip["PATTERN"] = 0xAA5555AA
self.chip["PATTERN"].write()
self.chip["CONTROL"]["PATTERN_EN"] = 1
self.chip["CONTROL"].write()
self.chip["CONTROL"]["PATTERN_EN"] = 0
self.chip["CONTROL"].write()
for _ in range(5):
self.chip["CONTROL"].write()
self.assertEqual(self.chip["fifo"].get_data().tolist(), [0xAA5555AA] * 35)
def test_direct(self):
self.chip["CONTROL"]["COUNTER_DIRECT"] = 1
self.chip["CONTROL"].write()
size = 648
base_data_addr = self.chip["fifo"]._conf["base_data_addr"]
ret = self.chip["intf"].read(base_data_addr, size=size)
ret = np.hstack((ret, self.chip["intf"].read(base_data_addr, size=size)))
x = np.arange(size * 2, dtype=np.uint8)
self.assertEqual(ret.tolist(), x.tolist())
def test_continouse(self):
self.chip["pulse"].set_delay(35)
self.chip["pulse"].set_width(3)
self.chip["pulse"].set_repeat(0)
self.chip["pulse"].start()
i = 0
error = False
for _ in range(100):
ret = self.chip["fifo"].get_data()
x = np.arange(i * 4, (i + ret.shape[0]) * 4, dtype=np.uint8)
x.dtype = np.uint32
i += ret.shape[0]
ok = np.alltrue(ret == x)
# print 'OK?', ok, ret.shape[0], i, k
if not ok:
error = True
break
self.assertFalse(error)
def tearDown(self):
self.chip.close() # let it close connection and stop simulator
cocotb_compile_clean()
