def setUp(self): fw_path = get_basil_dir() + "/firmware/modules" cocotb_compile_and_run( [ fw_path + "/gpio/gpio.v", fw_path + "/utils/reset_gen.v", fw_path + "/utils/bus_to_ip.v", fw_path + "/rrp_arbiter/rrp_arbiter.v", fw_path + "/utils/ODDR_sim.v", fw_path + "/utils/generic_fifo.v", fw_path + "/utils/cdc_pulse_sync.v", fw_path + "/utils/fx2_to_bus.v", fw_path + "/pulse_gen/pulse_gen.v", fw_path + "/pulse_gen/pulse_gen_core.v", fw_path + "/sram_fifo/sram_fifo_core.v", fw_path + "/sram_fifo/sram_fifo.v", os.path.dirname(__file__) + "/../firmware/src/sram_test.v", os.path.dirname(__file__) + "/../tests/tb.v", ], top_level="tb", sim_bus="basil.utils.sim.SiLibUsbBusDriver", ) with open(os.path.dirname(__file__) + "/../sram_test.yaml", "r") as f: cnfg = yaml.load(f) # change to simulation interface cnfg["transfer_layer"][0]["type"] = "SiSim" self.chip = Dut(cnfg) self.chip.init()
def setUp(self): sys.path = [os.path.dirname(os.getcwd())] + sys.path proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) cocotb_compile_and_run( sim_files = [proj_dir + '/test/mmc3_eth_tb.v'], top_level = 'tb', include_dirs = (proj_dir, proj_dir + '/src') ) ''' with open("test_mmc3_eth.yaml") as conf_file: try: conf = yaml.load(conf_file) except yaml.YAMLError as exception: print(exception) conf['transfer_layer'][0]['type'] self.chip = Dut(conf) self.chip.init() ''' self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): cocotb_compile_and_run([ os.path.join(os.path.dirname(__file__), 'test_SimTimestampDiv.v') ]) self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): extra_defines = [] root_dir = os.path.dirname(os.path.dirname( os.path.abspath(__file__))) # ../ tpx3_src = os.getenv("TPX3_SRC") if not tpx3_src: raise Exception( "Set TPX3_SRC variable. Point to TPX3 source direcotry!") cocotb_compile_and_run( sim_files=[root_dir + "/tests/tpx3_tb.v"], extra_defines=extra_defines, # sim_bus = 'basil.utils.sim.SiLibUsbBusDriver', include_dirs=(root_dir, root_dir + "/firmware/src", tpx3_src), extra="\nVSIM_ARGS += -t 1ps", #extra="\nVSIM_ARGS += -t 1ps -wlf /tmp/tpx3-daq.wlf\n", ) with open(root_dir + "/tpx3/tpx3.yml", "r") as f: cnfg = yaml.load(f, Loader=yaml.FullLoader) cnfg["transfer_layer"][0]["type"] = "SiSim" cnfg["transfer_layer"][0]["init"]["port"] = 12345 cnfg["transfer_layer"][0]["init"]["host"] = "localhost" self.chip = TPX3(conf=cnfg) self.chip.init()
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'), os.path.join(fw_path, 'utils/ODDR_sim.v'), os.path.join(fw_path, 'utils/generic_fifo.v'), os.path.join(fw_path, 'utils/cdc_pulse_sync.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(fw_path, 'pulse_gen/pulse_gen.v'), os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/sram_test.v'), os.path.join(os.path.dirname(__file__), '../tests/tb.v') ], top_level='tb', sim_bus='basil.utils.sim.SiLibUsbBusDriver') with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'), 'r') as f: cnfg = yaml.load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = Dut(cnfg) self.chip.init()
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'), os.path.join(fw_path, 'utils/ODDR_sim.v'), os.path.join(fw_path, 'utils/generic_fifo.v'), os.path.join(fw_path, 'utils/cdc_pulse_sync.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(fw_path, 'pulse_gen/pulse_gen.v'), os.path.join(fw_path, 'pulse_gen/pulse_gen_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/sram_test.v'), os.path.join(os.path.dirname(__file__), '../tests/tb.v')], top_level='tb', sim_bus='basil.utils.sim.SiLibUsbBusDriver' ) with open(os.path.join(os.path.dirname(__file__), '../sram_test.yaml'), 'r') as f: cnfg = yaml.load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = Dut(cnfg) self.chip.init()
def setUp(self): cocotb_compile_and_run(['test_SimTlu.v']) cnfg = yaml.load(cnfg_yaml) self.chip = Dut(cnfg) self.chip.init()
def setUp(self): sys.path = [os.path.dirname(os.getcwd())] + sys.path proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) cocotb_compile_and_run( sim_files=[proj_dir + '/test/bdaq53_eth_tb.v'], top_level='tb', include_dirs=(proj_dir, proj_dir + '/firmware/src') ) with open(proj_dir + '/bdaq53_eth.yaml') as conf_file: try: conf = yaml.safe_load(conf_file) except yaml.YAMLError as exception: print(exception) conf['transfer_layer'][0]['type'] = 'SiSim' conf['transfer_layer'][0]['tcp_connection'] = 'False' # conf['hw_drivers']['FIFO'] = ({'name': 'fifo', # 'type': 'sram_fifo', # 'interface': 'intf', # 'base_addr': 0x8000, # 'base_data_addr': 0x80000000}) conf['hw_drivers'].append({'name': 'FIFO', 'type': 'sram_fifo', 'interface': 'intf', 'base_addr': 0x8000, 'base_data_addr': 0x80000000}) self.chip = Dut(conf) self.chip.init()
def setUp(self): cocotb_compile_and_run([os.getcwd() + '/test_SimSeq.v']) cnfg = yaml.load(cnfg_yaml) self.chip = Dut(cnfg) self.chip.init()
def setUp(self): cocotb_compile_and_run( sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def) self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): cocotb_compile_and_run([ os.path.join(os.path.dirname(__file__), 'jtag_tap.v'), os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v') ]) self.chip = Dut(cnfg_yaml) self.chip.init(init_yaml)
def setUp(self): cocotb_compile_and_run([ os.path.join(os.path.dirname(__file__), 'jtag_tap.v'), os.path.join(os.path.dirname(__file__), 'test_SimJtagGpio.v')] ) self.chip = Dut(cnfg_yaml) self.chip.init(init_yaml)
def setUp(self): cocotb_compile_and_run( [ os.path.join(os.path.dirname(__file__), "jtag_tap.v"), os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v"), ] ) self.chip = Dut(cnfg_yaml) self.chip.init(init_yaml)
def setUp(self): proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) #../ verilog_src_fe65p2 = 'fe65p2.enc.sv' if os.path.isfile(proj_dir + '/tests/fe65p2.sv') : verilog_src_fe65p2 = 'fe65p2.sv' cocotb_compile_and_run( sim_files = [proj_dir + '/tests/fe65p2_tb.v', proj_dir + '/tests/' + verilog_src_fe65p2], extra_defines = ['TEST_DC=1'], sim_bus = 'basil.utils.sim.SiLibUsbBusDriver', include_dirs = (proj_dir, proj_dir + "/firmware/src"), extra = 'export SIMULATION_MODULES='+yaml.dump({'HitDefaultDriver' : {} }) )
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'gpio/gpio_core.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'), os.path.join(fw_path, 'utils/ODDR_sim.v'), os.path.join(fw_path, 'utils/generic_fifo.v'), os.path.join(fw_path, 'utils/cdc_pulse_sync.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(fw_path, 'utils/BUFG_sim.v'), os.path.join(fw_path, 'utils/cdc_syncfifo.v'), os.path.join(fw_path, 'utils/ddr_des.v'), os.path.join(fw_path, 'utils/IDDR_sim.v'), os.path.join(fw_path, 'utils/DCM_sim.v'), os.path.join(fw_path, 'utils/clock_divider.v'), os.path.join(fw_path, 'utils/clock_multiplier.v'), os.path.join(fw_path, 'utils/flag_domain_crossing.v'), os.path.join(fw_path, 'utils/3_stage_synchronizer.v'), os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx.v'), os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx_core.v'), os.path.join(fw_path, 'seq_gen/seq_gen.v'), os.path.join(fw_path, 'seq_gen/seq_gen_core.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/clk_gen.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'), os.path.join(os.path.dirname(__file__), '../tests/tb.v') ], top_level='tb', sim_bus='basil.utils.sim.SiLibUsbBusDriver') with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'), 'r') as f: cnfg = yaml.safe_load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = pixel.Pixel(cnfg) self.chip.init()
def setUp(self): root_dir = os.path.dirname(os.path.dirname( os.path.abspath(__file__))) #../ print root_dir cocotb_compile_and_run( sim_files=[root_dir + '/tests/lfcpix_tb.v'], sim_bus='basil.utils.sim.SiLibUsbBusDriver', include_dirs=(root_dir, root_dir + "/firmware/src"), ) with open(root_dir + '/lfcpix/lfcpix.yaml', 'r') as f: cnfg = yaml.load(f) cnfg['transfer_layer'][0]['type'] = 'SiSim' self.dut = lfcpix(conf=cnfg)
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'rrp_arbiter/rrp_arbiter.v'), os.path.join(fw_path, 'utils/ODDR_sim.v'), os.path.join(fw_path, 'utils/generic_fifo.v'), os.path.join(fw_path, 'utils/cdc_pulse_sync.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(fw_path, 'utils/BUFG_sim.v'), os.path.join(fw_path, 'utils/cdc_syncfifo.v'), os.path.join(fw_path, 'utils/ddr_des.v'), os.path.join(fw_path, 'utils/IDDR_sim.v'), os.path.join(fw_path, 'utils/DCM_sim.v'), os.path.join(fw_path, 'utils/clock_divider.v'), os.path.join(fw_path, 'utils/clock_multiplier.v'), os.path.join(fw_path, 'utils/flag_domain_crossing.v'), os.path.join(fw_path, 'utils/3_stage_synchronizer.v'), os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx.v'), os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx_core.v'), os.path.join(fw_path, 'seq_gen/seq_gen.v'), os.path.join(fw_path, 'seq_gen/seq_gen_core.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/clk_gen.v'), os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'), os.path.join(os.path.dirname(__file__), '../tests/tb.v')], top_level='tb', sim_bus='basil.utils.sim.SiLibUsbBusDriver' ) with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'), 'r') as f: cnfg = yaml.load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = pixel.Pixel(cnfg) self.chip.init()
def setUp(self): proj_dir = os.path.dirname(os.path.dirname( os.path.abspath(__file__))) #../ verilog_src_fe65_p2 = 'fe65p2.enc.sv' if os.path.isfile(proj_dir + '/tests/fe65p2.sv'): verilog_src_fe65_p2 = 'fe65p2.sv' cocotb_compile_and_run(sim_files=[ proj_dir + '/tests/fe65p2_tb.v', proj_dir + '/tests/' + verilog_src_fe65_p2 ], extra_defines=['TEST_DC=1'], sim_bus='basil.utils.sim.SiLibUsbBusDriver', include_dirs=(proj_dir, proj_dir + "/firmware/src"), extra='export SIMULATION_MODULES=' + yaml.dump({'HitDefaultDriver': {}}))
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(os.path.dirname(__file__), '../src/example.v')], top_level='example', sim_bus='basil.utils.sim.SiLibUsbBusDriver' ) with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f: cnfg = yaml.load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = Dut(cnfg) self.chip.init()
def setUp(self): fw_path = os.path.join(get_basil_dir(), 'firmware/modules') cocotb_compile_and_run([ os.path.join(fw_path, 'gpio/gpio.v'), os.path.join(fw_path, 'utils/reset_gen.v'), os.path.join(fw_path, 'utils/bus_to_ip.v'), os.path.join(fw_path, 'utils/fx2_to_bus.v'), os.path.join(os.path.dirname(__file__), '../src/example.v') ], top_level='example', sim_bus='basil.utils.sim.SiLibUsbBusDriver') with open(os.path.join(os.path.dirname(__file__), 'example.yaml'), 'r') as f: cnfg = yaml.safe_load(f) # change to simulation interface cnfg['transfer_layer'][0]['type'] = 'SiSim' self.chip = Dut(cnfg) self.chip.init()
def setUp(self): self.file_name = self.generate_data() cocotb_compile_and_run( [qmca_dir + "/tests/mca_tb.v"], sim_bus="basil.utils.sim.SiLibUsbBusDriver", include_dirs=(qmca_dir,), extra="export SIMULATION_MODULES=" + yaml.dump({"MCAFileDriver": {"file_name": str(self.file_name)}}), ) with open(qmca_dir + "/qmca.yaml", "r") as f: cnfg = yaml.load(f) cnfg["transfer_layer"][0]["type"] = "SiSim" cnfg["hw_drivers"][0]["init"]["no_calibration"] = True # this should be based on some search # cnfg['transfer_layer'].remove(cnfg['transfer_layer'][1]) # cnfg['hw_drivers'].remove(cnfg['hw_drivers'][1]) # cnfg['hw_drivers'].remove(cnfg['hw_drivers'][0]) # cnfg['registers'].remove(cnfg['registers'][5]) # cnfg['registers'].remove(cnfg['registers'][4]) # cnfg['registers'].remove(cnfg['registers'][3]) # cnfg['registers'].remove(cnfg['registers'][2]) # cnfg['registers'].remove(cnfg['registers'][1]) # cnfg['registers'].remove(cnfg['registers'][0]) self.ch = 0 # Channel to use self.ev = 0 # Event to use self.th = 2500 # Threshold self.my_qmca = qmca.qmca( config=cnfg, channel=self.ch, sample_count=self.sample_count, sample_delay=self.sample_delay, threshold=self.th, )
def setUp(self): fw_path = get_basil_dir() + "/firmware/modules" cocotb_compile_and_run( [ fw_path + "/gpio/gpio.v", fw_path + "/utils/reset_gen.v", fw_path + "/utils/bus_to_ip.v", fw_path + "/utils/fx2_to_bus.v", os.path.dirname(__file__) + "/../src/example.v", ], top_level="example", sim_bus="basil.utils.sim.SiLibUsbBusDriver", ) with open(os.path.dirname(__file__) + "/example.yaml", "r") as f: cnfg = yaml.load(f) # change to simulation interface cnfg["transfer_layer"][0]["type"] = "SiSim" self.chip = Dut(cnfg) self.chip.init()
def setUp(self): root_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) cocotb_compile_and_run(sim_bus="StreamDriver", sim_files=[root_dir + '/tests/tb.v'], include_dirs=(root_dir, root_dir + "/firmware/src", root_dir + "/tests")) with open(root_dir + '/pytlu/tlu.yaml', 'r') as f: cnfg = yaml.load(f) cnfg['transfer_layer'][0]['type'] = 'SiSim' cnfg['hw_drivers'].append({ 'name': 'SEQ_GEN_TB', 'type': 'seq_gen', 'interface': 'intf', 'base_addr': 0xc000 }) cnfg['hw_drivers'].append({ 'name': 'TLU_TB', 'type': 'tlu', 'interface': 'intf', 'base_addr': 0xf000 }) cnfg['hw_drivers'].append({ 'name': 'FIFO_TB', 'type': 'bram_fifo', 'interface': 'intf', 'base_addr': 0xf100, 'base_data_addr': 0x80000000 }) cnfg['hw_drivers'].append({ 'name': 'TDC_TB', 'type': 'tdc_s3', 'interface': 'intf', 'base_addr': 0xf200 }) cnfg['hw_drivers'].append({ 'name': 'VETO_PULSER_TB', 'type': 'pulse_gen', 'interface': 'intf', 'base_addr': 0xf300 }) seq_tracks = [{ 'name': 'T0', 'position': 0 }, { 'name': 'T1', 'position': 1 }, { 'name': 'T2', 'position': 2 }, { 'name': 'T3', 'position': 3 }] cnfg['registers'].append({ 'name': 'SEQ_TB', 'type': 'TrackRegister', 'hw_driver': 'SEQ_GEN_TB', 'seq_width': 8, 'seq_size': 8 * 1024, 'tracks': seq_tracks }) self.dut = Tlu(conf=cnfg) self.dut.init()
def setUp(self): cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimTlu.v')]) self.chip = Dut(cnfg_yaml) self.chip.init()
def sim_config(extra_defines=[]): if "SIM" not in os.environ.keys(): os.environ["SIM"] = "verilator" if os.environ["SIM"] == "verilator": hw_test_utils.patch_cocotb_makefile() # if hit_file is not None and len(hit_file) > 0: # os.environ['SIMULATION_MODULES'] = yaml.dump({'tjmonopix2_daq.sim.HitDataFile': { # 'filename': hit_file # }}) tjmonopix2_path = os.path.dirname(tjmonopix2.__file__) # tjmonopix2 package path top_dir = os.path.join( tjmonopix2_path, ".." ) # dir with firmware etc. that are not part of package basil_dir = os.path.dirname(basil.__file__) simulation_modules = {} simulation_modules["tjmonopix2.tests.test_hardware.drivers.Drive320Clock"] = {} os.environ["SIMULATION_MODULES"] = yaml.dump(simulation_modules) os.environ["SIMULATION_END_ON_DISCONNECT"] = "1" os.environ["COCOTB_REDUCED_LOG_FMT"] = "1" os.environ["SIMULATION_TRANSACTION_WAIT"] = str(25000 * 10) os.environ["SIMULATION_BUS_CLOCK"] = "0" # Find free port with socketserver.TCPServer(("localhost", 0), None) as s: free_port = s.server_address[1] os.environ["SIMULATION_PORT"] = str(free_port) version = utils.get_software_version().split(".") cocotb_compile_and_run( sim_files=[tjmonopix2_path + "/tests/test_hardware/hdl/tb.v"], top_level="tb", sim_bus="basil.utils.sim.BasilSbusDriver", include_dirs=( top_dir + "/firmware/src", top_dir + "/tjmonopix2/tests/test_hardware/hdl", basil_dir + "/firmware/modules", basil_dir + "/firmware/modules/utils", ), compile_args=[ "-DVERSION_MAJOR={:s}".format(version[0]), "-DVERSION_MINOR={:s}".format(version[1]), "-DVERSION_PATCH={:s}".format(version[2]), "-LDFLAGS {:s}/tjmonopix2/tests/test_hardware/hdl/libmonopix2.a".format(top_dir), "--hierarchical", "-Wno-COMBDLY", "-Wno-PINMISSING", "-Wno-fatal", "--output-split 15000", "-O3", "-CFLAGS -O3", ], build_args=[ "-j 2" ], extra_defines=extra_defines, extra="EXTRA_ARGS = --trace-fst --trace-structs", ) with open(os.path.join(tjmonopix2_path, "system", "bdaq53.yaml"), "r") as f: cnfg = yaml.full_load(f) cnfg["transfer_layer"][0]["type"] = "SiSim" cnfg["transfer_layer"][0]["init"]["host"] = "localhost" cnfg["transfer_layer"][0]["init"]["port"] = free_port cnfg["transfer_layer"][0]["init"]["timeout"] = 10000 cnfg["hw_drivers"][0] = { "name": "FIFO", "type": "bram_fifo", "interface": "intf", "base_addr": 0x8000, "base_data_addr": 0x80000000, } for item in cnfg["hw_drivers"]: if "pulse_gen640" in item["type"]: cnfg["hw_drivers"].remove(item) os.environ["SiSim"] = "1" return cnfg
def setUp(self): cocotb_compile_and_run([os.path.dirname(__file__) + '/test_SimI2c.v']) self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): cocotb_compile_and_run(['test_SimTlu.v']) self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): cocotb_compile_and_run([os.getcwd() + '/test_SimSpi.v']) self.chip = Dut(cnfg_yaml) self.chip.init()
def setUp(self): cocotb_compile_and_run([os.getcwd() + '/test_SimAdcRx.v']) self.chip = Dut(cnfg_yaml) self.chip.init()