def circuit(self):
super().circuit()
R = Resistor()
stiff_voltage = Divider(type='resistive')(V=self.V,
V_out=self.V_split +
0.6 @ u_V,
Load=self.I_b)
stiff_voltage.input += self.v_ref
stiff_voltage.gnd += self.gnd
stiff_voltage.v_ref += self.v_ref
splitter = Bipolar(type='npn', common='emitter',
follow='collector')(collector=R(self.R_out),
emitter=R(self.R_out))
split = stiff_voltage & self & splitter
self.output = Net('OutputInverse')
self.output_n += splitter.collector
self.output += splitter.emitter
R_in = R.parallel_sum(
R,
[self.R_out * 2, stiff_voltage.R_in, stiff_voltage.R_out]) @ u_Ohm
self.C_in = (1 / (2 * pi * self.f_3db * R_in)) @ u_F
signal = Net('VoltageShiftAcInput')
ac_coupling = signal & Capacitor()(self.C_in) & self.input
self.input = signal
def spi(self, instance):
"""
If additional devices are connected to the ISP lines, the programmer must be protected from any device
that may try to drive the lines, other than the AVR. This is important with the SPI bus, as it is similar to the
ISP interface. Applying series resistors on the SPI lines, as depicted in Connecting the SPI Lines to the
ISP Interface, is the easiest way to achieve this. Typically, the resistor value R can be of 330тДж
"""
mosi = Net('MOSI')
miso = Net('MISO')
sck = Net('SCK')
isp_mosi = self['MOSI'] & Resistor()(
330 @ u_Ohm) & mosi & instance['MOSI']
isp_miso = self['MISO'] & Resistor()(
330 @ u_Ohm) & miso & instance['MISO']
isp_sck = self['SCK'] & Resistor()(330 @ u_Ohm) & sck & instance['SCK']
for pin in ['MOSI', 'MISO', 'SCK']:
instance[pin].disconnect()
instance_pin = instance[pin]
instance_pin += self[pin]
self.MOSI = mosi
self.MISO = miso
self.SCK = sck
def circuit(self):
R = Resistor()
Gate = Bipolar(type='npn', follow='collector', common='emitter')
rectifier = Signal(clamp='rectifier')(V=self.V,
Load=self.Load,
frequency=self.frequency)
trigger = Gate(collector=R(self.R_load, ref='Trigger_Collector'),
base=R(self.R_load * 10, ref='Trigger_Base'))
pulse = Gate(collector=lambda T: Resistor()
((self.V - (T['VCE'] or 0.3) @ u_V) / self.I_load,
ref='Pulse_Collector'))
delay = Decay()(V=self.V,
V_out=self.V / 2,
Time_to_V_out=self.width,
Load=(self.V - trigger.V_je) /
(3 * self.I_load / pulse.Beta),
reverse=True)
self.v_ref & trigger.v_ref & pulse.v_ref
self.gnd & trigger.gnd & pulse.gnd & rectifier.gnd
self.input & rectifier & trigger.base
pulse & trigger & delay.gnd
self.v_ref & delay & pulse & self.output
def circuit(self):
super().circuit()
sensor = Bipolar(type='npn', common='emitter')(
base = Resistor()(self.R_sensor_in),
collector = Resistor()(self.R_sensor_collector),
)
holder = Bipolar(type='npn', common='emitter')(
base = Resistor()( self.R_holder_base)
)
holder.v_ref += sensor.output
holder.gnd += self.gnd
self.C_width = (self.width / self.R_pulse_base) * 1.4
pulsar_width = RLC(series='C', vref='R')(
C_series = self.C_width,
R_vref = self.R_pulse_base)
pulsar_width.v_ref += self.v_ref
pulsar = Bipolar(type='npn', common='emitter')(
base = pulsar_width,
collector = Resistor()(self.R_pulse_collector)
)
output = Net('onHightPulse')
pulse = self & sensor & pulsar & output & holder
self.output = output
def circuit(self):
for signal in self.inputs:
or_gate = Bipolar(type='npn', common='emitter',
follow='emitter')(collector=self.v_ref,
base=Resistor()(10000),
emitter=self.output)
signal & or_gate.input
pulldown = self.output & Resistor()(10000) & self.gnd
def circuit(self):
if self.R_in > 0 @ u_Ohm:
input = self.input & Resistor()(self.R_in) & self.output
else:
self.input & self.output
if self.R_out > 0 @ u_Ohm:
output = self.output & Resistor()(self.R_out) & self.gnd
else:
self.output & self.gnd
self.Power = self.R_in + self.R_out
self.consumption(self.V)
def circuit(self):
v_ref = self.v_ref
for signal in self.inputs:
and_input = Bipolar(type='npn',
follow='emitter')(collector=v_ref,
base=Resistor()(10000))
and_input.input += signal
v_ref = and_input.output
self.outputs = [v_ref]
pulldown = v_ref & Resistor()(10000) & self.gnd
def circuit(self):
new_outputs = []
for signal in self.inputs:
inverted = Net('LogicInverted')
inverter = Bipolar(type='npn', common='emitter', follow='collector')(
collector = Resistor()(1000),
base = Resistor()(10000)
)
inverter.v_ref += self.v_ref
inverter.gnd += self.gnd
circuit = signal & inverter & inverted
new_outputs.append(inverted)
self.outputs = new_outputs
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('GndResistorOutput')
R_gnd = signal & self.output & Resistor()(self.R_gnd) & self.gnd
def part_spice(self):
from skidl.pyspice import K
Transformer = {
'1': Net('TransformerInputP'),
'2': Net('TransformerInputN'),
'3': Net('TransformerOutputP'),
'4': Net('TransformerOutputN')
}
Spacer = Resistor()(value=1 @ u_Ohm)
# Lin = L(value=100 @ u_H)
Lin = RLC(series=['L', 'R'])(
R_series = 1 @ u_Ohm,
L_series = 10 @ u_H
)
Lout = RLC(series=['L', 'R'])(
R_series = 1 @ u_Ohm,
L_series = .5 @ u_H
)
primary = Transformer['1'] & Lin & Transformer['2']
secondary = Transformer['3'] & Lout & Transformer['4']
transformer = K(inductor1='L_s', inductor2='L_s_1', coupling_factor=self.coupling_factor)
return Transformer
def circuit(self):
"""
C_integrator -- `(integrator) = 1 / (2 * pi * (sensor) * (Frequency))`
"""
R = Resistor()
# Set R_input to a standard value
sensor = R(100 @ u_kOhm)
# Calculate C_integrator to set the unety-gain integration frequency.
integrator = Capacitor()(
(1 / (2 * pi * sensor.value * self.Frequency)) @ u_F)
# Calculate R_feedback to set the lower cutoff frequency a decade less than the minimum operating frequency
feedback = R(
(10 /
(2 * pi * integrator.value * self.Frequency / self.Q)) @ u_Ohm)
self.H = -1 / (sensor.value * integrator.value)
# Select an amplifier with a gain bandwidth at least 10 times the desired maximum operating frequency
buffer = OpAmp()(Frequency=self.Frequency * self.Q)
buffer.connect_power_bus(self)
self.input & sensor & buffer.input_n & (
feedback | integrator) & buffer.output & self.output
self.gnd & buffer.input
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('SeriesResistorOutput')
R_series = signal & Resistor()(self.R_series) & self.output
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('FilterLowpassOutput')
low_pass = signal & Resistor()(self.R_low) & self.output & Capacitor()(
self.C_pass) & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('FilterHighpassOutput')
high_pass = signal & Capacitor()(
self.C_block) & self.output & Resistor()(self.R_shunt) & self.gnd
def circuit(self):
R = Resistor()
self.emitter = R(self.R_e)
super().circuit()
# R_in -- `1/R_(i\\n) = 1/R_s + 1/R_g + 1 / R_(i\\n(base))`
stiff_voltage = Divider(type='resistive')(
V = self.V,
V_out = self.V_e + self.V_je,
Load = self.I_in
)
stiff_voltage.gnd & self.gnd
# Stiffed voltage
self.v_ref & stiff_voltage & self.input
self.R_in = R.parallel_sum(R, [self.R_in_base_dc, stiff_voltage.R_in, stiff_voltage.R_out])
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('SignalClampedOutput')
Rref = None
clamp = Diode(type='generic')()
if self.V_out and self.V and self.V > self.V_out:
Rref = Divider(type='resistive')(V=self.V,
V_out=self.V_out - clamp.V_j,
Load=self.I_load * 10)
Rref.gnd += self.gnd
else:
Rref = Resistor()(667)
self.v_ref & Rref & clamp['K', 'A'] & self.output
signal_input = signal & Resistor()(self.R_load / 3) & self.output
def circuit(self):
super().circuit()
rc = self \
& Resistor()(10000) \
& Bipolar(
type='npn',
common='emitter'
)(collector=self.load_block) & self.gnd
def circuit(self):
super().circuit()
R = Resistor()
D = Diode(type='generic')
signal = self.output
self.output = Net('SignalLimitedOutput')
limiter = signal & R(1000 @ u_Ohm) & self.output & (D() | D()) & self.v_ref
def test_body_kit(self):
from bem.basic import Resistor
from bem.basic.source import VS
load = Resistor()(V=self.block.V_load)
power = VS(flow='V')(V=5 @ u_V)
blocks = [
(load, { 'input': ['output'], 'output': ['v_ref'] })
]
def circuit(self, **kwargs):
# Some current must flow through the zener, so you choose `(V_(min) - V_(out))/R_(source) > I_(load)(max)`
source = Resistor()((self.V - self.V_out) / self.I_load / 10)
P_zener = (
(self.V - self.V_out) / source.value - self.I_load) * self.V_out
# The zener must be able to dissipate `P_(zen\er) = ((V - V_(out))/R_(source) - I_(load)) * V_(out)`
regulator = Diode(type='zener', BV=self.V_out, P=P_zener)()
self.input & source & self.output & regulator['K, A'] & self.gnd
def mirror(self, programmer):
self.R_g = (self.V - self.V_drop) / self.I_load
mirror = Bipolar(type='pnp', follow='collector', common='base')()
mirroring = mirror.base & programmer.base
generator = Resistor()(self.R_g)
sink = self.ref_input(
) & programmer & programmer.base & generator & self.gnd
load = self.ref_input() & mirror
return mirror.output
def circuit(self):
super().circuit()
rc = self \
& Resistor()(10000) \
& Bipolar(
type='pnp',
common='collector',
follow='collector'
)(collector = self.load_block) & self.gnd
def circuit(self):
period = 1 / self.Frequency
quant = period / 4
rate = self.V / quant
self.tau = u(self.V / rate)
discharger = Resistor()(self.R_load / 10)
integrator = Capacitor()((self.tau / discharger.value) @ u_F)
self.input & self.v_ref & discharger & self.output & integrator & self.gnd
def circuit(self):
period = 1 / self.Frequency
quant = period / 4
rate = self.V / quant
self.tau = u(self.V / rate)
current_sensing = Resistor()(self.R_load * 2)
differetiator = Capacitor()((self.tau / current_sensing.value) @ u_F)
self.input & self.v_ref & differetiator & self.output & current_sensing & self.gnd
def circuit(self):
super().circuit()
signal = self.output
self.output = Net('FilterTrapOutput')
rin = Resistor()(value=self.R_trap, ref='R_in')
lc = RLC(series=['L', 'C'])(L_series=self.L_notch,
C_series=self.C_notch)
lc.output += self.gnd
circuit = signal & rin & (self.output | lc.input)
def mirror(self, programmer):
mirror = Bipolar(type='pnp', follow='collector', common='base')()
stabilizer = Bipolar(type='pnp', follow='collector', common='base')()
mirroring = mirror.base & programmer.base & stabilizer
self.R_g = (self.V - stabilizer.V_je) / self.I_load
generator = Resistor()(self.R_g)
sink = self.ref_input(
) & programmer & stabilizer.base & generator & self.gnd
v_ref = self.ref_input() & mirror
return stabilizer.output
def circuit(self):
current_source = Resistor()(self.R_load / 2)
discharger = Capacitor()(
(self.Time_to_V_out / (current_source.value * log(self.V / (self.V - self.V_out)))) @ u_F
)
if self.reverse:
self.input & current_source & self.output
self.gnd & discharger & self.output
else:
self.input & current_source & self.output & discharger & self.gnd
def circuit(self):
super().circuit()
"""
The reset line has an internal pull-up resistor. If the environment is noisy, it can be insufficient and reset
may occur sporadically. Refer to the device datasheet for the value of the pull-up resistor that must be
used for specific devices.
"""
pull_up = self['RESET'] & Resistor()(4.7 @ u_kOhm) & self.v_ref
"""
If an external switch is connected to the RESET pin, it is important to add a series resistance. Whenever
the switch is pressed, it will short the capacitor and the current (I) through the switch can have high peak
values. This causes the switch to bounce and generate steep spikes in 2ms - 10ms (t) periods until the
capacitor is discharged. The PCB tracks and the switch metal introduces a small inductance (L) and the
high current through these tracks can generate high voltages up to `VL = L * dI/dt`.
This spike voltage VL is most likely outside the specification of the RESET pin. By adding a series resistor
between the switch and the capacitor, the peak currents generated will be significantly low and it will not
be large enough to generate high voltages at the RESET pin. An example connection is shown in the
following diagram.
"""
reset = self['RESET'] & Resistor()(
330 @ u_Ohm, V=1) & Switch(input='physical')() & self.gnd
"""
To protect the RESET line from further noise, connect a capacitor from the RESET pin to ground. This is
not directly required since the AVR internally have a low-pass filter to eliminate spikes and noise that
could cause reset. Using an extra capacitor is an additional protection. However, such extra capacitor
cannot be used when DebugWIRE or PDI is used.
"""
noise_protect = self['RESET'] & Capacitor()(100 @ u_nF) & self.gnd
"""
ESD protection diode is not provided internally from RESET to VCC in order to allow HVPP. If HVPP is not
used, it is recommended to add an ESD protection diode externally from RESET to VCC. Alternatively, a
Zener diode can be used to limit the RESET voltage relative to GND. A Zener diode is highly
recommended in noisy environments. The components should be located physically close to the RESET
pin of the AVR.Recommended circuit of a RESET line is shown in the following circuit diagram.
"""
esd_protection = self['RESET'] & Diode(
type='generic')()['A, K'] & self.v_ref
def circuit(self):
super().circuit()
output = Net('FilterBandpassOutput')
# Sink resistor
R_band = Resistor()(self.R_band)
# Inductor tanker
L_tank = Inductor()(self.L_tank)
C_tank = Capacitor()(self.C_tank)
# Filter Network
self & R_band & output & (L_tank | C_tank) & self.gnd
self.output = output
def circuit(self):
R = Resistor()
amplifier = OpAmp()(frequency=self.Frequency)
self.v_ref & amplifier.v_ref
self.v_inv & amplifier.gnd
# Using high-value resistors can degrade the phase margin of the circuit and introduce additional noise in the circuit.
feedback = R(
self.R_load * 10
) # Common principle to use much larger input impeadance compared to load before amplifier TODO: Why?
source = R(feedback.value / (self.Gain - 1))
self.input & amplifier.input
self.gnd & source & amplifier.input_n & feedback & amplifier.output & self.output
