DIG_IP_START = '10.100.0.70'
DIG_MAC_START = '02:02:00:00:00:01'
DIG_TX_PORT = 8888
DIG_TX_IP_START = '239.0.0.68'
if args.start and args.stop:
raise RuntimeError('Start and stop?')
# make the fpga host
fdig = KatcpFpga(DIG_HOST)
print 'Connected to %s.' % fdig.host
if args.program:
stime = time.time()
fdig.upload_to_ram_and_program(DIG_BOF)
print 'Programmed %s in %.2f seconds.' % (fdig.host, time.time() - stime)
# stop sending data
fdig.registers.control.write(gbe_txen=False)
# start the local timer on the test d-engine - mrst, then a fake sync
fdig.registers.control.write(mrst='pulse')
fdig.registers.control.write(msync='pulse')
# the all_fpgas have tengbe cores, so set them up
ip_bits = DIG_IP_START.split('.')
ipbase = int(ip_bits[3])
mac_bits = DIG_MAC_START.split(':')
macbase = int(mac_bits[5])
for ctr in range(0, 4):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=DIG_TX_PORT)
