def digitiser_stop(): print 'Stopping digitiser' fdig = KatcpClientFpga(dhost) if fdig.is_running(): fdig.test_connection() fdig.get_system_information() fdig.registers.control.write(gbe_txen = False) fdig.deprogram() fdig.disconnect()
def digitiser_start(dig_tx_tuple): fdig = KatcpClientFpga(dhost) fdig.deprogram() stime = time.time() print 'Programming digitiser', sys.stdout.flush() fdig.upload_to_ram_and_program(dbof) print time.time() - stime fdig.test_connection() fdig.get_system_information() # stop sending data fdig.registers.control.write(gbe_txen = False) # start the local timer on the test d-engine - mrst, then a fake sync fdig.registers.control.write(mrst = 'pulse') fdig.registers.control.write(msync = 'pulse') # the all_fpgas have tengbe cores, so set them up ip_bits = dip_start.split('.') ipbase = int(ip_bits[3]) mac_bits = dmac_start.split(':') macbase = int(mac_bits[5]) for ctr in range(0,4): mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr) ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr) fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=7777) for gbe in fdig.tengbes: gbe.tap_start(True) # set the destination IP and port for the tx txaddr = dig_tx_tuple[0] txaddr_bits = txaddr.split('.') txaddr_base = int(txaddr_bits[3]) txaddr_prefix = '%s.%s.%s.' % (txaddr_bits[0], txaddr_bits[1], txaddr_bits[2]) print 'digitisers sending to: %s%d port %d' % (txaddr_prefix, txaddr_base + 0, dig_tx_tuple[2]) fdig.write_int('gbe_iptx0', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 0))) fdig.write_int('gbe_iptx1', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 1))) fdig.write_int('gbe_iptx2', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 2))) fdig.write_int('gbe_iptx3', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 3))) fdig.write_int('gbe_porttx', dig_tx_tuple[2]) fdig.registers.control.write(gbe_rst=False) # enable the tvg on the digitiser and set up the pol id bits fdig.registers.control.write(tvg_select0=True) fdig.registers.control.write(tvg_select1=True) fdig.registers.id2.write(pol1_id=1) # start tx print 'Starting dig TX...', sys.stdout.flush() fdig.registers.control.write(gbe_txen=True) print 'done.' sys.stdout.flush() fdig.disconnect()
polltime = args.polltime num_spead_headers = 4 xeng_hosts = args.hosts.lstrip().rstrip().replace(' ', '').split(',') xeng_hosts = ['roach020921', 'roach020927', 'roach020919', 'roach020925', 'roach02091a', 'roach02091e', 'roach020923', 'roach020924'] # create the devices and connect to them xfpgas = [] for host in xeng_hosts: xeng_fpga = KatcpClientFpga(host) time.sleep(0.3) if not xeng_fpga.is_connected(): xeng_fpga.connect() xeng_fpga.test_connection() xeng_fpga.get_system_information() numgbes = len(xeng_fpga.tengbes) if numgbes < 1: raise RuntimeError('Cannot have an xengine with no 10gbe cores?') print '%s: found %i 10gbe core%s.' % (host, numgbes, '' if numgbes == 1 else 's') xfpgas.append(xeng_fpga) def print_headers(scr): '''Print the table headers. ''' scr.addstr(2, 2, 'xhost') scr.addstr(2, 20, 'tap') scr.addstr(2, 30, 'TX') scr.addstr(3, 30, 'cnt') scr.addstr(3, 40, 'err')
if program: setup_gbe = True for fpga in all_fpgas: fpga.deprogram() ftuple = [(fdig, dfpg)] ftuple.extend([(fpga, ffpg) for fpga in ffpgas]) ftuple.extend([(fpga, xfpg) for fpga in xfpgas]) stime = time.time() print 'Programming: ', sys.stdout.flush() misc.program_fpgas(ftuple, timeout=45) print time.time() - stime ftuple = None for fpga in all_fpgas: fpga.test_connection() fpga.get_system_information() if setup_gbe: # stop sending data fdig.registers.control.write(gbe_txen=False) for fpga in ffpgas: fpga.registers.control.write(gbe_txen=False) for fpga in xfpgas: fpga.registers.control.write(gbe_txen=False) # pulse the cores reset lines from False to True fdig.registers.control.write(gbe_rst = False) for fpga in ffpgas: fpga.registers.control.write(gbe_rst = False) for fpga in xfpgas: