def _con(self, scope=None, bsfile=None, force=False, fpga_id=None):
"""Connect to CW305 board, and download bitstream.
If the target has already been programmed it skips reprogramming
unless forced.
Args:
scope (ScopeTemplate): An instance of a scope object.
bsfile (path): The path to the bitstream file to program the FPGA with.
force (bool): Whether or not to force reprogramming.
fpga_id (string): '100t', '35t', or None. If bsfile is None and fpga_id specified,
program with AES firmware for fpga_id
"""
from datetime import datetime
self._naeusb.con(idProduct=[0xC305])
if not fpga_id is None:
if fpga_id not in ('100t', '35t'):
raise ValueError(f"Invalid fpga {fpga_id}")
self._fpga_id = fpga_id
if self.fpga.isFPGAProgrammed() == False or force:
if bsfile is None:
if not fpga_id is None:
from chipwhisperer.hardware.firmware.cw305 import getsome
bsdata = getsome(f"AES_{fpga_id}.bit")
starttime = datetime.now()
status = self.fpga.FPGAProgram(bsdata,
exceptOnDoneFailure=False)
stoptime = datetime.now()
if status:
logging.info('FPGA Config OK, time: %s' %
str(stoptime - starttime))
else:
logging.warning(
'FPGA Done pin failed to go high, check bitstream is for target device.'
)
else:
print("No FPGA Bitstream file specified.")
elif not os.path.isfile(bsfile):
print(("FPGA Bitstream not configured or '%s' not a file." %
str(bsfile)))
else:
starttime = datetime.now()
status = self.fpga.FPGAProgram(open(bsfile, "rb"),
exceptOnDoneFailure=False)
stoptime = datetime.now()
if status:
logging.info('FPGA Config OK, time: %s' %
str(stoptime - starttime))
else:
logging.warning(
'FPGA Done pin failed to go high, check bitstream is for target device.'
)
self.usb_clk_setenabled(True)
self.fpga_write(0x100 + self._woffset, [0])
self.pll.cdce906init()
def spi_mode(self, enable=True, timeout=200, bsfile=None):
"""Enter programming mode for the onboard SPI chip
Reprograms the FPGA with the appropriate bitstream and
returns an object with which to program the CW305 SPI chip
(see documentation on the returned object for more info)
Args:
enable (bool): Enable the SPI interface before returning it. Defaults to True
timeout (int): USB timeout in ms. Defaults to 200.
bsfile (string): If not None, program with a bitstream pointed to by bsfile.
If None, program with SPI passthrough bitstream for the chip
specified during connection (or cw.target())
Returns:
A FPGASPI object which can be used to erase/program/verify/read the SPI
chip on the CW305.
"""
from datetime import datetime
if self._fpga_id is None and bsfile is None:
logging.warning(
"CW305 requires passthrough bitstream to program SPI chip, but file/chip not specified"
)
else:
bsdata = None
if self._fpga_id:
from chipwhisperer.hardware.firmware.cw305 import getsome
bsdata = getsome(f"SPI_flash_{self._fpga_id}.bit")
else:
bsdata = open(bsfile, "rb")
starttime = datetime.now()
status = self.fpga.FPGAProgram(bsdata, exceptOnDoneFailure=False)
stoptime = datetime.now()
if status:
logging.info('FPGA Config OK, time: %s' %
str(stoptime - starttime))
else:
logging.warning(
'FPGA Done pin failed to go high, check bitstream is for target device.'
)
spi = FPGASPI(self._naeusb, timeout)
spi.enable_interface(enable)
return spi
def _con(self,
scope=None,
bsfile=None,
force=False,
fpga_id=None,
defines_files=None,
slurp=True):
# add more stuff later
self._naeusb.con(idProduct=[0xC310])
# self.pll.cdce906init()
if defines_files is None:
if fpga_id is None:
verilog_defines = [self.default_verilog_defines_full_path]
else:
from chipwhisperer.hardware.firmware.cw305 import getsome
verilog_defines = [getsome(self.default_verilog_defines)]
else:
verilog_defines = defines_files
if slurp:
self.slurp_defines(verilog_defines)
if bsfile:
status = self.fpga.FPGAProgram(open(bsfile, "rb"))
def _con(self,
scope=None,
bsfile=None,
force=False,
fpga_id=None,
defines_files=None,
slurp=True):
"""Connect to CW305 board, and download bitstream.
If the target has already been programmed it skips reprogramming
unless forced.
Args:
scope (ScopeTemplate): An instance of a scope object.
bsfile (path): The path to the bitstream file to program the FPGA with.
force (bool): Whether or not to force reprogramming.
fpga_id (string): '100t', '35t', or None. If bsfile is None and fpga_id specified,
program with AES firmware for fpga_id
defines_files (list, optional): path to cw305_defines.v
slurp (bool, optional): Whether or not to slurp the Verilog defines.
"""
from datetime import datetime
self._naeusb.con(idProduct=[0xC305])
if not fpga_id is None:
if fpga_id not in ('100t', '35t'):
raise ValueError(f"Invalid fpga {fpga_id}")
self._fpga_id = fpga_id
if self.fpga.isFPGAProgrammed() == False or force:
if bsfile is None:
if not fpga_id is None:
from chipwhisperer.hardware.firmware.cw305 import getsome
if self.target_name == 'AES':
bsdata = getsome(f"AES_{fpga_id}.bit")
elif self.target_name == 'Cryptech ecdsa256-v1 pmul':
bsdata = getsome(f"ECDSA256v1_pmul_{fpga_id}.bit")
starttime = datetime.now()
status = self.fpga.FPGAProgram(bsdata,
exceptOnDoneFailure=False)
stoptime = datetime.now()
if status:
logging.info('FPGA Config OK, time: %s' %
str(stoptime - starttime))
else:
logging.warning(
'FPGA Done pin failed to go high, check bitstream is for target device.'
)
else:
print("No FPGA Bitstream file specified.")
elif not os.path.isfile(bsfile):
print(("FPGA Bitstream not configured or '%s' not a file." %
str(bsfile)))
else:
starttime = datetime.now()
status = self.fpga.FPGAProgram(open(bsfile, "rb"),
exceptOnDoneFailure=False)
stoptime = datetime.now()
if status:
logging.info('FPGA Config OK, time: %s' %
str(stoptime - starttime))
else:
logging.warning(
'FPGA Done pin failed to go high, check bitstream is for target device.'
)
self.usb_clk_setenabled(True)
self.pll.cdce906init()
if defines_files is None:
if fpga_id is None:
verilog_defines = [self.default_verilog_defines_full_path]
else:
from chipwhisperer.hardware.firmware.cw305 import getsome
verilog_defines = [getsome(self.default_verilog_defines)]
else:
verilog_defines = defines_files
if slurp:
self.slurp_defines(verilog_defines)