def setUp(self):
self.s27 = cg.strip_blackboxes(cg.from_lib("s27"))
self.s27bb = cg.from_lib("s27")
# incorrect copy of s27
self.s27m = cg.copy(self.s27)
self.s27m.graph.nodes["n_11"]["type"] = "and"
def test_verilog_output(self):
for g in [
cg.from_lib("test_correct_io", name="test_module_0"),
cg.from_lib("test_correct_io", name="test_module_1"),
cg.from_lib("test_correct_io", name="test_module_2"),
cg.from_lib("test_correct_io", name="test_module_3"),
]:
g2 = verilog_to_circuit(circuit_to_verilog(g), g.name)
m = miter(g, g2)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
if different_output:
import code
code.interact(local=dict(globals(), **locals()))
self.assertFalse(different_output)
def test_kcuts(self):
c = cg.from_lib("c432")
for n in c:
for cut in c.kcuts(n, 2):
clc = cg.copy(c)
for g in cut:
clc.disconnect(clc.fanin(g), g)
clc.set_type(g, "input")
self.assertSetEqual(clc.startpoints(n), cut)
def test_bench_output(self):
g = cg.from_lib(f"b17_C")
g2 = cg.bench_to_circuit(cg.circuit_to_bench(g), g.name)
m = miter(g, g2)
live = sat(m)
self.assertTrue(live)
different_output = sat(m, assumptions={"sat": True})
self.assertFalse(different_output)
def test_bench(self):
g = cg.from_lib(f"b17_C")
self.assertEqual(len(g), 2943)
self.assertSetEqual(g.fanin("n2905"), set(["n2516", "n2904"]))
self.assertSetEqual(g.fanin("out789"), set(["out789_driver"]))
self.assertSetEqual(g.fanin("out789_driver"), set(["n2942"]))
self.assertSetEqual(g.fanout("in382"), set(["n2484"]))
self.assertEqual(g.type("n2905"), "and")
self.assertEqual(g.type("out789"), "output")
self.assertEqual(g.type("out789_driver"), "not")
self.assertEqual(g.type("in382"), "input")
def test_subcircuit(self):
c17 = cg.from_lib("c17")
sc = subcircuit(c17, c17.transitive_fanin("N22") | {"N22"})
self.assertSetEqual(
sc.nodes(),
{"N22", "N22_driver", "N10", "N16", "N1", "N3", "N2", "N11", "N6"},
)
self.assertSetEqual(
sc.edges(),
{
("N22_driver", "N22"),
("N10", "N22_driver"),
("N16", "N22_driver"),
("N1", "N10"),
("N3", "N10"),
("N2", "N16"),
("N11", "N16"),
("N3", "N11"),
("N6", "N11"),
},
)
for node in sc:
self.assertEqual(c17.type(node), sc.type(node))
def test_verilog_seq(self):
g = cg.from_lib("test_correct_io", name="test_module_2")
self.assertSetEqual(
g.nodes(),
set([
"clk",
"G0",
"G1",
"\\G2[0]",
"\\G2[1]",
"\\G18[0]",
"\\G18[1]",
"G3",
"G4",
"G5",
]),
)
self.assertSetEqual(g.fanin("G4"), set(["G3"]))
self.assertSetEqual(g.fanin("G5"), set(["\\G2[0]"]))
self.assertSetEqual(g.fanin("\\G18[0]"), set(["G5"]))
self.assertSetEqual(set(g.clk(["G4", "G5", "\\G18[0]"])), set(["clk"]))
self.assertEqual(g.d("G4"), "G3")
self.assertSetEqual(set(g.type(["G4", "G5", "\\G18[0]"])), set(["ff"]))
def test_verilog_escaped_names(self):
g = cg.from_lib("test_correct_io", name="test_module_3")
self.assertSetEqual(
g.nodes(),
set([
"clk",
"\\G0[0]",
"\\I0[0]",
"\\I0[1]",
"\\G1[1][0]",
"\\G1[1][1]",
"\\G2[0]",
"\\G3[0][0]",
"\\G3[0][1]",
"\\G3[0][2]",
"\\I1[0]",
"\\not_G1[1][1]",
"\\and_G0[0]_not_G1[1][1]",
]),
)
self.assertSetEqual(g.fanin("\\G2[0]"),
set(["\\G0[0]", "\\G1[1][1]", "\\I0[1]"]))
self.assertSetEqual(g.fanin("\\G3[0][0]"),
set(["\\G0[0]", "\\G1[1][0]"]))
def setUp(self):
self.s27 = cg.strip_blackboxes(cg.from_lib("s27"))
if n not in mapping and n in mapping.values():
if all(s not in mapping and s in mapping.values()
for s in cl.fanout(n)):
cl.remove(n)
deleted = True
# node in net fanout
if n in [mapping[o] for o in net_outs] and n in cl:
cl.remove(n)
deleted = True
cg.lint(cl)
return cl, key
if __name__ == '__main__':
# load circuit from library
c = cg.from_lib('c432')
# lock
cl, key = lebl(c, 16, 3)
# check equiv
m = cg.miter(c, cl)
# rename key for use in miter
keym = {f'c1_{k}': v for k, v in key.items()}
if not cg.sat(m, keym):
print('not live')
if cg.sat(m, {**keym, 'sat': True}):
print('not equiv')
#write
#cg.to_file(cl,'c432_lebl.v')
def setUpClass(cls):
cls.c17 = cg.from_lib("c17_gates")
cls.s27 = cg.from_lib("s27")
def test_verilog_comb(self):
for g in [
cg.from_lib("test_correct_io", name="test_module_0"),
cg.from_lib("test_correct_io", name="test_module_1"),
]:
self.assertSetEqual(
g.nodes(),
set([
"G1",
"G2",
"G3",
"G4",
"\\G5[0]",
"\\G5[1]",
"G17",
"G18",
"G19",
"G20",
"G21",
"\\G22[0]",
"\\G22[1]",
"\\G8[0]",
"\\G8[1]",
"not_G2",
"xor_G3_G4",
"and_G1_G2",
"tie_1",
"\\and_G8[0]_G5[0]",
"or_not_G2_tie_1",
]),
)
self.assertSetEqual(g.fanin("\\G8[0]"), set(["G1", "G3"]))
self.assertSetEqual(g.fanin("G17"), set(["\\G8[1]", "tie_1"]))
self.assertSetEqual(g.fanin("G18"), set(["G2", "\\G5[0]"]))
self.assertSetEqual(g.fanin("\\G22[0]"), set(["\\G5[1]", "G4"]))
self.assertEqual(g.type("\\G8[0]"), "nand")
self.assertEqual(g.type("G17"), "nor")
self.assertEqual(g.type("G18"), "and")
self.assertEqual(g.type("\\G22[0]"), "xor")
self.assertEqual(g.type("tie_1"), "1")
self.assertSetEqual(g.fanin("G19"), set(["and_G1_G2",
"xor_G3_G4"]))
self.assertSetEqual(g.fanin("and_G1_G2"), set(["G1", "G2"]))
self.assertSetEqual(g.fanin("xor_G3_G4"), set(["G3", "G4"]))
self.assertSetEqual(g.fanin("G20"),
set(["G17", "\\and_G8[0]_G5[0]"]))
self.assertSetEqual(g.fanin("\\and_G8[0]_G5[0]"),
set(["\\G8[0]", "\\G5[0]"]))
self.assertSetEqual(g.fanin("\\G22[1]"),
set(["G1", "or_not_G2_tie_1"]))
self.assertSetEqual(g.fanin("or_not_G2_tie_1"),
set(["not_G2", "tie_1"]))
self.assertSetEqual(g.fanin("not_G2"), set(["G2"]))
self.assertSetEqual(
g.inputs(), set(["G1", "G2", "G3", "G4", "\\G5[0]",
"\\G5[1]"]))
self.assertSetEqual(
g.outputs(),
set([
"G17", "G18", "G19", "G20", "G21", "\\G22[0]", "\\G22[1]"
]),
)
def test_topo_sort(self):
c = cg.from_lib("c432")
visited = set()
for n in c.topo_sort():
self.assertFalse(c.transitive_fanout(n) & visited)
visited.add(n)
def setUp(self):
self.s27 = cg.from_lib("s27")
# incorrect copy of s27
self.s27m = self.s27.copy()
self.s27m.graph.nodes["n_11"]["type"] = "buf"