def __init__(self, config, signals, clk, *, clk_freq=None):
self.log = SimLog("cocomod.uart.{}".format(self.__class__.__name__))
self.config = config
self.clk = clk.signal
if clk_freq is None:
clk_freq = 1 / get_time_from_sim_steps(clk.period, "sec")
self.divisor = round(clk_freq / config.baud)
self.duration = clk.period * self.divisor
self.tx = signals.tx
self.rx = signals.rx
self.ctsn = signals.ctsn
self.rtsn = signals.rtsn
if config.flow_control == UARTFlowControl.HARDWARE and self.ctsn is None:
raise RuntimeError(
"HARDWARE flow control selected and no CTS signal")
if config.flow_control == UARTFlowControl.HARDWARE and self.rtsn is None:
raise RuntimeError(
"HARDWARE flow control selected and no RTS signal")
self.tx <= 1
if self.ctsn is not None:
self.ctsn <= 1
Driver.__init__(self)
Monitor.__init__(self)
def __init__(self, name, dut_clock, dut_data, dut_addr, dut_config_en):
self.name = name
self.clock = dut_clock
self.data_port = dut_data
self.addr_port = dut_addr
self.en_port = dut_config_en
Driver.__init__(self)
self.reset()
def __init__(self, name, dut_clock, dut_data, dut_req, dut_ack):
self.name = name
self.clock = dut_clock
self.data_port = dut_data
self.req_port = dut_req
self.ack_port = dut_ack
Driver.__init__(self)
self._reset()
def __init__(self, signals, clk):
self.log = SimLog("cocomod.fifointerface.%s" % (self.__class__.__name__))
self.valid = signals.valid
self.ready = signals.ready
self.data = signals.data
self.clk = clk.signal
self.valid <= 0
Driver.__init__(self)
def __init__(self,
fifo_block,
clock,
block_name,
io_enum,
write_out=True,
out_dir=""):
FifoWrapper.__init__(self, fifo_block, clock, block_name, io_enum,
write_out, out_dir)
Driver.__init__(self)
def __init__(self, config, signals, clk, *, clk_freq=None):
self.log = logging.getLogger("cocotbext.spi.{}".format(self.__class__.__name__))
self.log.setLevel(config.loglevel)
self.config = config
self.clk = clk
if clk_freq is None:
clk_freq = 1 / get_time_from_sim_steps(clk.period, "sec")
self.miso = signals.miso
self.mosi = signals.mosi
self.cs = signals.cs
self.sclk = signals.sclk
# chip select Edging
if self.config.csphase:
self.csBeginEdge = RisingEdge(self.cs)
self.csEndEdge = FallingEdge(self.cs)
else:
self.csBeginEdge = FallingEdge(self.cs)
self.csEndEdge = RisingEdge(self.cs)
# sclk edging
# CPOL | leading edge | trailing edge
# ------|--------------|--------------
# false | rising | falling
# true | falling | rising
if self.config.cpol:
self.sclkLeadEdge = FallingEdge(self.sclk)
self.sclkTrailEdge = RisingEdge(self.sclk)
else:
self.sclkLeadEdge = RisingEdge(self.sclk)
self.sclkTrailEdge = FallingEdge(self.sclk)
# CPHA | data change | data read
# ------|----------------|--------------
# false | trailling edge | leading edge
# true | leading edge | trailing edge
if self.config.cpha:
self.dataChangEdge = self.sclkLeadEdge
self.dataReadEdge = self.sclkTrailEdge
else:
self.dataChangEdge = self.sclkTrailEdge
self.dataReadEdge = self.sclkLeadEdge
Driver.__init__(self)
Monitor.__init__(self)
def __init__(self, signal, clock, interleaved=True):
"""Args:
signal (SimHandle): The XGMII data bus.
clock (SimHandle): The associated clock (assumed to be
driven by another coroutine).
interleaved (bool, optional): Whether control bits are interleaved
with the data bytes or not.
If interleaved the bus is
byte0, byte0_control, byte1, byte1_control, ...
Otherwise expect
byte0, byte1, ..., byte0_control, byte1_control, ...
"""
self.log = signal._log
self.signal = signal
self.clock = clock
self.bus = _XGMIIBus(len(signal) // 9, interleaved=interleaved)
Driver.__init__(self)
def __init__(self, signal, clock, interleaved=True):
"""Args:
signal (SimHandle): The xgmii data bus.
clock (SimHandle): The associated clock (assumed to be
driven by another coroutine).
interleaved (bool, optional): Whether control bits are interleaved
with the data bytes or not.
If interleaved the bus is
byte0, byte0_control, byte1, byte1_control, ...
Otherwise expect
byte0, byte1, ..., byte0_control, byte1_control, ...
"""
self.log = signal._log
self.signal = signal
self.clock = clock
self.bus = _XGMIIBus(len(signal)/9, interleaved=interleaved)
Driver.__init__(self)
def __init__(self, dut):
self.dut = dut
Driver.__init__(self)
def __init__(self, entity, regfile):
self.dut = entity
self.regfile = regfile
self.irqs = self.regfile.get_rtl_irq_inputs()
Driver.__init__(self)
self._reset()
def __init__(self, dut):
self.dut = dut
Driver.__init__(self)
