class TB(object): def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", cq_straddle=False, cc_straddle=False, rq_straddle=False, rc_straddle=False, rc_4tlp_straddle=False, pf_count=1, max_payload_size=1024, enable_client_tag=True, enable_extended_tag=True, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, pf0_msi_enable=True, pf0_msi_count=32, pf1_msi_enable=False, pf1_msi_count=1, pf2_msi_enable=False, pf2_msi_count=1, pf3_msi_enable=False, pf3_msi_count=1, pf0_msix_enable=False, pf0_msix_table_size=0, pf0_msix_table_bir=0, pf0_msix_table_offset=0x00000000, pf0_msix_pba_bir=0, pf0_msix_pba_offset=0x00000000, pf1_msix_enable=False, pf1_msix_table_size=0, pf1_msix_table_bir=0, pf1_msix_table_offset=0x00000000, pf1_msix_pba_bir=0, pf1_msix_pba_offset=0x00000000, pf2_msix_enable=False, pf2_msix_table_size=0, pf2_msix_table_bir=0, pf2_msix_table_offset=0x00000000, pf2_msix_pba_bir=0, pf2_msix_pba_offset=0x00000000, pf3_msix_enable=False, pf3_msix_table_size=0, pf3_msix_table_bir=0, pf3_msix_table_offset=0x00000000, pf3_msix_pba_bir=0, pf3_msix_pba_offset=0x00000000, # signals # Clock and Reset Interface user_clk=dut.clk, user_reset=dut.rst, # user_lnk_up # sys_clk # sys_clk_gt # sys_reset # phy_rdy_out # Requester reQuest Interface rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, # pcie_rq_tag0 # pcie_rq_tag1 # pcie_rq_tag_av # pcie_rq_tag_vld0 # pcie_rq_tag_vld1 # Requester Completion Interface rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), # Completer reQuest Interface cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), # pcie_cq_np_req # pcie_cq_np_req_count # Completer Completion Interface cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), # Transmit Flow Control Interface # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, # Configuration Management Interface cfg_mgmt_addr=dut.cfg_mgmt_addr, cfg_mgmt_function_number=dut.cfg_mgmt_function_number, cfg_mgmt_write=dut.cfg_mgmt_write, cfg_mgmt_write_data=dut.cfg_mgmt_write_data, cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, cfg_mgmt_read=dut.cfg_mgmt_read, cfg_mgmt_read_data=dut.cfg_mgmt_read_data, cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, # cfg_mgmt_debug_access # Configuration Status Interface # cfg_phy_link_down # cfg_phy_link_status # cfg_negotiated_width # cfg_current_speed cfg_max_payload=dut.cfg_max_payload, cfg_max_read_req=dut.cfg_max_read_req, # cfg_function_status # cfg_vf_status # cfg_function_power_state # cfg_vf_power_state # cfg_link_power_state # cfg_err_cor_out # cfg_err_nonfatal_out # cfg_err_fatal_out # cfg_local_error_out # cfg_local_error_valid # cfg_rx_pm_state # cfg_tx_pm_state # cfg_ltssm_state # cfg_rcb_status # cfg_obff_enable # cfg_pl_status_change # cfg_tph_requester_enable # cfg_tph_st_mode # cfg_vf_tph_requester_enable # cfg_vf_tph_st_mode # Configuration Received Message Interface # cfg_msg_received # cfg_msg_received_data # cfg_msg_received_type # Configuration Transmit Message Interface # cfg_msg_transmit # cfg_msg_transmit_type # cfg_msg_transmit_data # cfg_msg_transmit_done # Configuration Flow Control Interface cfg_fc_ph=dut.cfg_fc_ph, cfg_fc_pd=dut.cfg_fc_pd, cfg_fc_nph=dut.cfg_fc_nph, cfg_fc_npd=dut.cfg_fc_npd, cfg_fc_cplh=dut.cfg_fc_cplh, cfg_fc_cpld=dut.cfg_fc_cpld, cfg_fc_sel=dut.cfg_fc_sel, # Configuration Control Interface # cfg_hot_reset_in # cfg_hot_reset_out # cfg_config_space_enable # cfg_dsn # cfg_bus_number # cfg_ds_port_number # cfg_ds_bus_number # cfg_ds_device_number # cfg_ds_function_number # cfg_power_state_change_ack # cfg_power_state_change_interrupt cfg_err_cor_in=dut.status_error_cor, cfg_err_uncor_in=dut.status_error_uncor, # cfg_flr_in_process # cfg_flr_done # cfg_vf_flr_in_process # cfg_vf_flr_func_num # cfg_vf_flr_done # cfg_pm_aspm_l1_entry_reject # cfg_pm_aspm_tx_l0s_entry_disable # cfg_req_pm_transition_l23_ready # cfg_link_training_enable # Configuration Interrupt Controller Interface # cfg_interrupt_int # cfg_interrupt_sent # cfg_interrupt_pending cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status=dut. cfg_interrupt_msi_pending_status, cfg_interrupt_msi_pending_status_data_enable=dut. cfg_interrupt_msi_pending_status_data_enable, # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, # cfg_interrupt_msix_enable # cfg_interrupt_msix_mask # cfg_interrupt_msix_vf_enable # cfg_interrupt_msix_vf_mask # cfg_interrupt_msix_address # cfg_interrupt_msix_data # cfg_interrupt_msix_int # cfg_interrupt_msix_vec_pending # cfg_interrupt_msix_vec_pending_status # cfg_interrupt_msix_sent # cfg_interrupt_msix_fail cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, # Configuration Extend Interface # cfg_ext_read_received # cfg_ext_write_received # cfg_ext_register_number # cfg_ext_function_number # cfg_ext_write_data # cfg_ext_write_byte_enable # cfg_ext_read_data # cfg_ext_read_data_valid ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.dev.functions[0].configure_bar( 0, 2**len( dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr)) self.dev.functions[0].configure_bar( 2, 2**len( dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr)) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) async def init(self): await FallingEdge(self.dut.rst) await Timer(100, 'ns') await self.rc.enumerate() dev = self.rc.find_device(self.dev.functions[0].pcie_id) await dev.enable_device() await dev.set_master() await dev.alloc_irq_vectors(32, 32)
class TB(object): def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = S10PcieDevice( # configuration options pcie_generation=3, # pcie_link_width=8, # pld_clk_frequency=250e6, l_tile=False, pf_count=1, max_payload_size=1024, enable_extended_tag=True, pf0_msi_enable=True, pf0_msi_count=32, pf1_msi_enable=False, pf1_msi_count=1, pf2_msi_enable=False, pf2_msi_count=1, pf3_msi_enable=False, pf3_msi_count=1, pf0_msix_enable=False, pf0_msix_table_size=0, pf0_msix_table_bir=0, pf0_msix_table_offset=0x00000000, pf0_msix_pba_bir=0, pf0_msix_pba_offset=0x00000000, pf1_msix_enable=False, pf1_msix_table_size=0, pf1_msix_table_bir=0, pf1_msix_table_offset=0x00000000, pf1_msix_pba_bir=0, pf1_msix_pba_offset=0x00000000, pf2_msix_enable=False, pf2_msix_table_size=0, pf2_msix_table_bir=0, pf2_msix_table_offset=0x00000000, pf2_msix_pba_bir=0, pf2_msix_pba_offset=0x00000000, pf3_msix_enable=False, pf3_msix_table_size=0, pf3_msix_table_bir=0, pf3_msix_table_offset=0x00000000, pf3_msix_pba_bir=0, pf3_msix_pba_offset=0x00000000, # signals # Clock and reset # npor=dut.npor, # pin_perst=dut.pin_perst, # ninit_done=dut.ninit_done, # pld_clk_inuse=dut.pld_clk_inuse, # pld_core_ready=dut.pld_core_ready, reset_status=dut.rst, # clr_st=dut.clr_st, # refclk=dut.refclk, coreclkout_hip=dut.clk, # RX interface rx_bus=S10RxBus.from_prefix(dut, "rx_st"), # TX interface tx_bus=S10TxBus.from_prefix(dut, "tx_st"), # TX flow control tx_ph_cdts=dut.tx_ph_cdts, tx_pd_cdts=dut.tx_pd_cdts, tx_nph_cdts=dut.tx_nph_cdts, tx_npd_cdts=dut.tx_npd_cdts, tx_cplh_cdts=dut.tx_cplh_cdts, tx_cpld_cdts=dut.tx_cpld_cdts, tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed, tx_data_cdts_consumed=dut.tx_data_cdts_consumed, tx_cdts_type=dut.tx_cdts_type, tx_cdts_data_value=dut.tx_cdts_data_value, # Hard IP status # int_status=dut.int_status, # int_status_common=dut.int_status_common, # derr_cor_ext_rpl=dut.derr_cor_ext_rpl, # derr_rpl=dut.derr_rpl, # derr_cor_ext_rcv=dut.derr_cor_ext_rcv, # derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv, # rx_par_err=dut.rx_par_err, # tx_par_err=dut.tx_par_err, # ltssmstate=dut.ltssmstate, # link_up=dut.link_up, # lane_act=dut.lane_act, # currentspeed=dut.currentspeed, # Power management # pm_linkst_in_l1=dut.pm_linkst_in_l1, # pm_linkst_in_l0s=dut.pm_linkst_in_l0s, # pm_state=dut.pm_state, # pm_dstate=dut.pm_dstate, # apps_pm_xmt_pme=dut.apps_pm_xmt_pme, # apps_ready_entr_l23=dut.apps_ready_entr_l23, # apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff, # app_init_rst=dut.app_init_rst, # app_xfer_pending=dut.app_xfer_pending, # Interrupt interface app_msi_req=dut.app_msi_req, app_msi_ack=dut.app_msi_ack, app_msi_tc=dut.app_msi_tc, app_msi_num=dut.app_msi_num, app_msi_func_num=dut.app_msi_func_num, # app_int_sts=dut.app_int_sts, # Error interface # app_err_valid=dut.app_err_valid, # app_err_hdr=dut.app_err_hdr, # app_err_info=dut.app_err_info, # app_err_func_num=dut.app_err_func_num, # Configuration output tl_cfg_func=dut.tl_cfg_func, tl_cfg_add=dut.tl_cfg_add, tl_cfg_ctl=dut.tl_cfg_ctl, # Configuration extension bus # ceb_req=dut.ceb_req, # ceb_ack=dut.ceb_ack, # ceb_addr=dut.ceb_addr, # ceb_din=dut.ceb_din, # ceb_dout=dut.ceb_dout, # ceb_wr=dut.ceb_wr, # ceb_cdm_convert_data=dut.ceb_cdm_convert_data, # ceb_func_num=dut.ceb_func_num, # ceb_vf_num=dut.ceb_vf_num, # ceb_vf_active=dut.ceb_vf_active, # Hard IP reconfiguration interface # hip_reconfig_clk=dut.hip_reconfig_clk, # hip_reconfig_address=dut.hip_reconfig_address, # hip_reconfig_read=dut.hip_reconfig_read, # hip_reconfig_readdata=dut.hip_reconfig_readdata, # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid, # hip_reconfig_write=dut.hip_reconfig_write, # hip_reconfig_writedata=dut.hip_reconfig_writedata, # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest, ) # self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.dev.functions[0].configure_bar( 0, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst. axil_ctrl_awaddr)) self.dev.functions[0].configure_bar( 2, 2**len( dut.example_core_pcie_s10_inst.core_pcie_inst.axi_ram_awaddr)) async def init(self): await FallingEdge(self.dut.rst) await Timer(100, 'ns') await self.rc.enumerate() dev = self.rc.find_device(self.dev.functions[0].pcie_id) await dev.enable_device() await dev.set_master() await dev.alloc_irq_vectors(32, 32)