def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*1000)
SdramTester("sdramTester",phaseManager,Stream(dut,"io_bus_cmd"),Stream(dut,"io_bus_rsp"),dut.clk,dut.reset)
yield phaseManager.run()
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*2000)
checker = Axi4SharedMemoryChecker("checker",phaseManager,Axi4Shared(dut, "io_axi"),12,dut.clk,dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 2000))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
DriverAgent("driver", phaseManager, dut)
MonitorAgent("monitor", phaseManager, dut)
yield phaseManager.run()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 1000)
SdramTester("sdramTester", phaseManager, Stream(dut, "io_bus_cmd"),
Stream(dut, "io_bus_rsp"), dut.clk, dut.reset)
yield phaseManager.run()
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*200)
StreamFifoTester("fifoA",phaseManager,Stream(dut,"fifoAPush"),Stream(dut,"fifoAPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure()
StreamFifoTester("fifoB",phaseManager,Stream(dut,"fifoBPush"),Stream(dut,"fifoBPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure()
yield phaseManager.run()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 2000)
checker = Axi4SharedMemoryChecker("checker", phaseManager,
Axi4Shared(dut, "io_axi"), 12, dut.clk,
dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
def test1(dut):
random.seed(0)
from cocotblib.misc import cocotbXHack
cocotbXHack()
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
StreamFifoTester("fifoA", phaseManager, Stream(dut, "fifoAPush"),
Stream(dut, "fifoAPop"), bundleAGen, 3000, dut.clk,
dut.reset).createInfrastructure()
StreamFifoTester("fifoB", phaseManager, Stream(dut, "fifoBPush"),
Stream(dut, "fifoBPop"), bundleAGen, 3000, dut.clk,
dut.reset).createInfrastructure()
yield phaseManager.run()
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*200)
checker = Axi4SharedMemoryChecker("checker",phaseManager,Axi4Shared(dut, "io_axi"),12,dut.clk,dut.reset)
checker.idWidth = 2
checker.nonZeroReadRspCounterTarget = 2000
yield phaseManager.run()
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
cocotb.fork(SimulationTimeout(1000 * 8000))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
driver = DriverAgent("driver", phaseManager, dut)
monitor = MonitorAgent("monitor", phaseManager, dut)
for i in range(1 << 8):
dut.io_memWrite_valid <= 1
dut.io_memWrite_payload_address <= i
dut.io_memWrite_payload_data <= randBits(32)
yield RisingEdge(dut.clk)
dut.io_memWrite_valid <= 0
driver.memInitDone = True
yield phaseManager.run()
def test1(dut):
random.seed(0)
import time
clkTocken = [1000]
sock = socket.socket(
socket.AF_INET, # Internet
socket.SOCK_DGRAM) # UDP
sock.setsockopt(SOL_SOCKET, SO_REUSEADDR, 1)
sock.setsockopt(SOL_SOCKET, SO_BROADCAST, 1)
sock.bind(('', SERVER_PORT))
cocotb.fork(ClockDomainAsyncResetTokened(dut.clk, dut.reset, clkTocken))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 200)
DriverAgent("driver", phaseManager, dut, sock, clkTocken)
MonitorAgent("monitor", phaseManager, dut, sock)
yield phaseManager.run()
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000*2000)
axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(2)]
axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(2)]
axiReadOnlyMasters = [Axi4ReadOnly(dut, "axiReadOnlyMasters_" + str(i)) for i in range(2)]
axiReadOnlySlaves = [Axi4ReadOnly(dut, "axiReadOnlySlaves_" + str(i)) for i in range(2)]
axiWriteOnlyMasters = [Axi4WriteOnly(dut, "axiWriteOnlyMasters_" + str(i)) for i in range(2)]
axiWriteOnlySlaves = [Axi4WriteOnly(dut, "axiWriteOnlySlaves_" + str(i)) for i in range(2)]
axiSharedMasters = [Axi4Shared(dut, "axiSharedMasters_" + str(i)) for i in range(2)]
axiSharedSlaves = [Axi4Shared(dut, "axiSharedSlaves_" + str(i)) for i in range(2)]
# Instanciate master sides
for idx,axiMaster in enumerate(axiMasters):
WriteOnlyMasterDriver("Axi4WriteMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterDriver("Axi4ReadMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterMonitor("Axi4ReadMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
WriteOnlyMasterMonitor("Axi4WriteMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiMaster in enumerate(axiReadOnlyMasters):
ReadOnlyMasterDriver("ReadOnlyMasterDriver" + str(idx),phaseManager,4 + idx * 4, axiMaster, dut).createInfrastructure()
ReadOnlyMasterMonitor("ReadOnlyMasterMonitor" + str(idx),phaseManager,axiMaster,dut).createInfrastructure()
for idx,axiMaster in enumerate(axiWriteOnlyMasters):
WriteOnlyMasterDriver("WriteOnlyMasterDriver" + str(idx),phaseManager,8 + idx * 4, axiMaster, dut).createInfrastructure()
WriteOnlyMasterMonitor("WriteOnlyMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiMaster in enumerate(axiSharedMasters):
SharedMasterDriver("SharedMasterDriver" + str(idx),phaseManager,12 + idx * 4, axiMaster, dut).createInfrastructure()
SharedMasterMonitor("SharedMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiSlaves):
WriteOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure()
ReadOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure()
WriteDataMonitor("Axi4DataSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiReadOnlySlaves):
ReadOnlySlaveDriver(axiSlave,0x2000 + idx*0x0800,0x0800, dut).createInfrastructure()
for idx,axiSlave in enumerate(axiWriteOnlySlaves):
WriteOnlySlaveDriver(axiSlave,0x3000 + idx*0x0800,0x0800, dut).createInfrastructure()
WriteDataMonitor("WriteOnlySlaveMonitor" + str(idx),phaseManager,axiSlave,dut).createInfrastructure()
for idx,axiSlave in enumerate(axiSharedSlaves):
SharedSlaveDriver(axiSlave,0x1000 + idx*0x0800,0x0800, dut).createInfrastructure()
SharedDataMonitor("SharedSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure()
# cocotb.log.error("miaou")
# Run until completion
yield phaseManager.run()
# yield Timer(1000*6000)
dut.log.info("Cocotb test done")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
phaseManager = PhaseManager()
phaseManager.setWaitTasksEndTime(1000 * 2000)
axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(2)]
axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(2)]
axiReadOnlyMasters = [
Axi4ReadOnly(dut, "axiReadOnlyMasters_" + str(i)) for i in range(2)
]
axiReadOnlySlaves = [
Axi4ReadOnly(dut, "axiReadOnlySlaves_" + str(i)) for i in range(2)
]
axiWriteOnlyMasters = [
Axi4WriteOnly(dut, "axiWriteOnlyMasters_" + str(i)) for i in range(2)
]
axiWriteOnlySlaves = [
Axi4WriteOnly(dut, "axiWriteOnlySlaves_" + str(i)) for i in range(2)
]
axiSharedMasters = [
Axi4Shared(dut, "axiSharedMasters_" + str(i)) for i in range(2)
]
axiSharedSlaves = [
Axi4Shared(dut, "axiSharedSlaves_" + str(i)) for i in range(2)
]
# Instanciate master sides
for idx, axiMaster in enumerate(axiMasters):
WriteOnlyMasterDriver("Axi4WriteMasterDriver" + str(idx), phaseManager,
0 + idx * 4, axiMaster,
dut).createInfrastructure()
ReadOnlyMasterDriver("Axi4ReadMasterDriver" + str(idx), phaseManager,
0 + idx * 4, axiMaster,
dut).createInfrastructure()
ReadOnlyMasterMonitor("Axi4ReadMasterMonitor" + str(idx), phaseManager,
axiMaster, dut).createInfrastructure()
WriteOnlyMasterMonitor("Axi4WriteMasterMonitor" + str(idx),
phaseManager, axiMaster,
dut).createInfrastructure()
for idx, axiMaster in enumerate(axiReadOnlyMasters):
ReadOnlyMasterDriver("ReadOnlyMasterDriver" + str(idx), phaseManager,
4 + idx * 4, axiMaster,
dut).createInfrastructure()
ReadOnlyMasterMonitor("ReadOnlyMasterMonitor" + str(idx), phaseManager,
axiMaster, dut).createInfrastructure()
for idx, axiMaster in enumerate(axiWriteOnlyMasters):
WriteOnlyMasterDriver("WriteOnlyMasterDriver" + str(idx), phaseManager,
8 + idx * 4, axiMaster,
dut).createInfrastructure()
WriteOnlyMasterMonitor("WriteOnlyMasterMonitor" + str(idx),
phaseManager, axiMaster,
dut).createInfrastructure()
for idx, axiMaster in enumerate(axiSharedMasters):
SharedMasterDriver("SharedMasterDriver" + str(idx), phaseManager,
12 + idx * 4, axiMaster,
dut).createInfrastructure()
SharedMasterMonitor("SharedMasterMonitor" + str(idx), phaseManager,
axiMaster, dut).createInfrastructure()
for idx, axiSlave in enumerate(axiSlaves):
WriteOnlySlaveDriver(axiSlave, 0x0000 + idx * 0x0800, 0x0800,
dut).createInfrastructure()
ReadOnlySlaveDriver(axiSlave, 0x0000 + idx * 0x0800, 0x0800,
dut).createInfrastructure()
WriteDataMonitor("Axi4DataSlaveMonitor" + str(idx), phaseManager,
axiSlave, dut).createInfrastructure()
for idx, axiSlave in enumerate(axiReadOnlySlaves):
ReadOnlySlaveDriver(axiSlave, 0x2000 + idx * 0x0800, 0x0800,
dut).createInfrastructure()
for idx, axiSlave in enumerate(axiWriteOnlySlaves):
WriteOnlySlaveDriver(axiSlave, 0x3000 + idx * 0x0800, 0x0800,
dut).createInfrastructure()
WriteDataMonitor("WriteOnlySlaveMonitor" + str(idx), phaseManager,
axiSlave, dut).createInfrastructure()
for idx, axiSlave in enumerate(axiSharedSlaves):
SharedSlaveDriver(axiSlave, 0x1000 + idx * 0x0800, 0x0800,
dut).createInfrastructure()
SharedDataMonitor("SharedSlaveMonitor" + str(idx), phaseManager,
axiSlave, dut).createInfrastructure()
# cocotb.log.error("miaou")
# Run until completion
yield phaseManager.run()
# yield Timer(1000*6000)
dut.log.info("Cocotb test done")