def p_entity(p): '''entity : ENTITY IDENTIFIER IS portDef END IDENTIFIER SCOLON | ENTITY IDENTIFIER IS END IDENTIFIER SCOLON''' ident = p[2] inSignals = [] outSignals = [] # Entity does not contain a portDef if len(p) == 7: p[0] = vhdl.component(ident) return # Organize the signals # NOTE: inout ports not supported at the moment for signal in p[4]: if signal.type == 'in': inSignals.append(signal) elif signal.type == 'out': outSignals.append(signal) else: raise Exception("Invalid signal type.") #Create the entity #Note: an entity is identical to a component, however, its signals has global context p[0] = vhdl.component(ident, inSignals, outSignals)
def p_entity(p): '''entity : ENTITY IDENTIFIER IS portDef END IDENTIFIER SCOLON | ENTITY IDENTIFIER IS END IDENTIFIER SCOLON''' ident = p[2] inSignals = [] outSignals = [] # Entity does not contain a portDef if len(p) == 7: p[0] = vhdl.component(ident) return #Organize the signals for signal in p[4]: if signal.type == 'in': inSignals.append(signal) elif signal.type == 'out': outSignals.append(signal) else: raise Exception("Invalid signal type.") #Create the entity #Note: an entity is identical to a component, however, its signals has global context p[0] = vhdl.component(ident, inSignals, outSignals)
def p_component(p): 'component : COMPONENT IDENTIFIER portDef END COMPONENT SCOLON' #locals ident = p[2] inSignals = [] outSignals = [] #Organize the signals for signal in p[3]: if signal.type == 'in': inSignals.append(signal) elif signal.type == 'out': outSignals.append(signal) else: raise Exception("Invalid signal type.") #Create the component p[0] = vhdl.component(ident, inSignals, outSignals)