dhost = FpgaDsimHost(dig_host, config=dsim_conf)
print 'Connected to %s.' % dhost.host
if args.start and args.stop:
raise RuntimeError('Start and stop? You must be crazy!')
something_happened = False
if args.program:
dhost.initialise()
something_happened = True
else:
dhost.get_system_information()
if args.deprogram:
dhost.deprogram()
something_happened = True
print 'Deprogrammed %s.' % dhost.host
if args.resync:
print 'Reset digitiser timer and sync timer'
dhost.data_resync()
something_happened = True
if args.start:
# start tx
print 'Starting TX on %s' % dhost.host,
sys.stdout.flush()
dhost.enable_data_output(enabled=True)
dhost.registers.control.write(gbe_txen=True)
print 'done.'
dfpga.get_system_information(bitstream)
# # TODO HACK
# if 'gbecontrol' in dfpga.registers.names():
# dfpga.registers.gbecontrol.write_int(15)
# if 'gbecontrol' in dfpga.registers.names():
# dfpga.registers.gbecontrol.write_int(15)
# TODO HACK
if 'cwg0_en' in dfpga.registers.names():
dfpga.registers.cwg0_en.write(en=1)
dfpga.registers.cwg1_en.write(en=1)
# /HACK
if args.deprogram:
dfpga.deprogram()
something_happened = True
print('Deprogrammed {}.'.format(dfpga.host))
if args.resync:
dfpga.data_resync()
sync_epoch = time.time()
something_happened = True
print('Reset digitiser timer and sync timer: {}'.format(sync_epoch))
if args.start:
# start tx
print('Starting TX on {}'.format(dfpga.host))
sys.stdout.flush()
dfpga.enable_data_output(enabled=True)
dfpga.registers.control.write(gbe_txen=True)
