def main():
devices = database.get_devices()
for family in sorted(devices["families"].keys()):
for device in sorted(devices["families"][family]["devices"].keys()):
output_file = path.join(database.get_db_subdir(family, device),
"tilegrid.json")
subprocess.check_call(["./get_device_tilegrid.sh", device])
extract_tilegrid.main([
"extract_tilegrid", device, "../minitests/simple/wire.dump",
output_file
])
def extract_fuses(infile, architecture, part):
frames = 0
bits_per_frame = 0
with open(infile, "rt") as fin:
for line in fin:
frames = frames + 1
bits_per_frame = len(line.strip())
data = {}
data["frames"] = frames
data["bits"] = bits_per_frame
output_file = path.join(database.get_db_subdir(architecture, part),
"fuses.json")
with open(output_file, "wt") as fout:
json.dump(data, fout, sort_keys=True, indent=4)
def extract_fuses(infile, architecture, part):
rows = 0
cols = 0
with open(infile, "rt") as fin:
for line in fin:
rows = rows + 1
cols = len(line.strip())
data = {}
data["rows"] = rows
data["cols"] = cols
output_file = path.join(database.get_db_subdir(architecture, part),
"fuses.json")
with open(output_file, "wt") as fout:
json.dump(data, fout, sort_keys=True, indent=4)
def main():
shutil.rmtree("work_tilegrid", ignore_errors=True)
os.mkdir("work_tilegrid")
shutil.copy(
path.join(database.get_trellis_root(), "minitests", "wire", "wire.v"),
"work_tilegrid/wire.v")
for family in sorted(devices.families.keys()):
for device in sorted(devices.families[family]["devices"].keys()):
diamond.run(device, "work_tilegrid/wire.v")
output_file = path.join(database.get_db_subdir(family, device),
"tilegrid.json")
extract_tilegrid.main([
"extract_tilegrid", "work_tilegrid/wire.tmp/output.test",
output_file
])
def main():
devices = database.get_devices()
tang_root = database.get_tangdinasty_root()
for architecture in devices["architectures"].keys():
print("Architecture: " + architecture)
for part in devices["architectures"][architecture]["parts"].keys():
print("Part: " + part)
selected_part = devices["architectures"][architecture]["parts"][
part]
package = selected_part["packages"][0]
json_file = path.join(database.get_db_subdir(architecture, part),
"tilegrid.json")
chipdb = path.join(tang_root, "arch", part + ".db")
unlogic.decode_chipdb([
"get_tilegrid_all", chipdb, "--tilegrid", json_file,
"--datadir",
path.join("work_decrypt", part)
])
def main():
devices = database.get_devices()
tang_root = database.get_tangdinasty_root()
shutil.rmtree(database.get_db_root(), ignore_errors=True)
os.mkdir(database.get_db_root())
shutil.copy(path.join(database.get_tang_root(), "devices.json"), path.join(database.get_db_root(), "devices.json"))
for family in devices["families"].keys():
print("Family: " + family)
for device in devices["families"][family]["devices"].keys():
print("Device: " + device)
selected_device = devices["families"][family]["devices"][device]
database_dir = database.get_db_subdir(family, device)
if not path.exists(path.join(database_dir,"bits")):
os.mkdir(path.join(database_dir,"bits"))
chipdb = path.join(tang_root, "arch", device + ".db")
unlogic.decode_chipdb(["create_database", chipdb, "--db_dir", database_dir])
def main():
devices = database.get_devices()
for architecture in devices["architectures"].keys():
for part in devices["architectures"][architecture]["parts"].keys():
shutil.rmtree("work_tilegrid", ignore_errors=True)
os.mkdir("work_tilegrid")
selected_part = devices["architectures"][architecture]["parts"][
part]
package = selected_part["packages"][0]
max_row = int(selected_part["max_row"])
max_col = int(selected_part["max_col"])
prepare_tcl(
path.join(database.get_tang_root(), "minitests", "tilegrid",
"wire.tcl"), "work_tilegrid/wire.tcl", part, package)
prepare_pnl(architecture, part, package, max_row, max_col)
tangdinasty.run("wire.tcl", "work_tilegrid")
tiles = [[0 for y in range(max_col)] for x in range(max_row)]
extract_elements("work_tilegrid/wire.log", tiles, max_row)
file_loc = path.join(database.get_tang_root(), "minitests",
"tilegrid", part + ".v")
if os.path.exists(file_loc):
shutil.copyfile(file_loc,
path.join("work_tilegrid", part + ".v"))
prepare_tcl(
path.join(database.get_tang_root(), "minitests",
"tilegrid", "specific.tcl"),
"work_tilegrid/specific.tcl", part, package)
tangdinasty.run("specific.tcl", "work_tilegrid")
extract_elements("work_tilegrid/" + part + ".log", tiles,
max_row)
output_file = path.join(database.get_db_subdir(architecture, part),
"tilegrid.json")
with open(output_file, "wt") as fout:
json.dump(tiles, fout, sort_keys=True, indent=4)
extract_fuses("work_tilegrid/wire.fuse", architecture, part)
def main(argv: List[str]) -> None:
import argparse
import json
parser = argparse.ArgumentParser(
"Convert a .bit file into a .v verilog file for simulation")
parser.add_argument("bitfile", help="Input .bit file")
parser.add_argument(
"--package",
help="Physical package (e.g. CABGA256), for renaming I/O ports")
parser.add_argument(
"--lpf",
help="Use LOCATE COMP commands from this LPF file to name I/O ports")
parser.add_argument("-n",
"--module-name",
help="Name for the top-level module (default: top)",
default="top")
args = parser.parse_args(argv)
if args.lpf and not args.package:
parser.error(
"Cannot use a LPF file without specifying the chip package")
pytrellis.load_database(database.get_db_root())
print("Loading bitstream...", file=sys.stderr)
bitstream = pytrellis.Bitstream.read_bit(args.bitfile)
chip = bitstream.deserialise_chip()
if args.package:
dbfn = os.path.join(
database.get_db_subdir(chip.info.family, chip.info.name),
"iodb.json")
with open(dbfn, "r") as f:
iodb = json.load(f)
if args.lpf:
lpf_map = parse_lpf(args.lpf)
else:
lpf_map = {}
# Rename PIO and IOLOGIC BELs based on their connected pins, for readability
mod_renames = {}
for pin_name, pin_data in iodb["packages"][args.package].items():
if pin_name in lpf_map:
# escape LPF name in case it has funny characters
pin_name = "\\" + lpf_map[pin_name]
# PIO and IOLOGIC do not share pin names except for IOLDO/IOLTO
mod_renames["R{row}C{col}_PIO{pio}".format(
**pin_data)] = f"{pin_name}"
mod_renames["R{row}C{col}_IOLOGIC{pio}".format(
**pin_data)] = f"{pin_name}"
# Note: the mod_name_map only affects str(node), not node.mod_name
Node.mod_name_map = mod_renames
print("Computing routing graph...", file=sys.stderr)
rgraph = chip.get_routing_graph()
print("Computing connection graph...", file=sys.stderr)
tiles_by_loc = make_tiles_by_loc(chip)
graph = gen_config_graph(chip, rgraph, tiles_by_loc)
print("Generating Verilog...", file=sys.stderr)
print_verilog(graph, tiles_by_loc, args.module_name)
print("Done!", file=sys.stderr)
