def setUp(self):
# obligatory and optional ports
g = DeltaGraph()
out_port_obl = OutPort(
'out',
Int(),
InPort(None, Int(), None, 0),
RealNode(g, [], name='node_name'),
)
out_port_opt = OutPort(
'out',
Int(),
InPort(None, Optional(Int()), None, 0),
RealNode(g, [], name='node_name'),
)
# 4 types of queues
self.delta_queue_obl = DeltaQueue(out_port_obl)
self.delta_queue_opt = DeltaQueue(out_port_opt)
self.const_queue_obl = ConstQueue(out_port_obl)
self.const_queue_opt = ConstQueue(out_port_opt)
# test messages
self.msg1 = QueueMessage(1)
self.msg2 = QueueMessage(2)
self.msg_with_none = QueueMessage(None)
self.msg_unpackable = QueueMessage("abcde")
# these messages should be received
self.msg1_answer = QueueMessage(1)
self.msg2_answer = QueueMessage(2)
self.msg_with_none_answer = QueueMessage(None)
def setUp(self):
# obligatory and optional ports
out_port_obl = OutPort(
NamespacedName("port_name", None),
DInt(),
InPort(NamespacedName("port_name", None),
DInt(), None, 0),
None
)
out_port_opt = OutPort(
NamespacedName("port_name", None),
DInt(),
InPort(NamespacedName("port_name", None),
DOptional(DInt()), None, 0),
None
)
# 4 types of queues
self.delta_queue_obl = DeltaQueue(out_port_obl)
self.delta_queue_opt = DeltaQueue(out_port_opt)
self.const_queue_obl = ConstQueue(out_port_obl)
self.const_queue_opt = ConstQueue(out_port_opt)
# test messages
self.msg1 = QueueMessage(1)
self.msg2 = QueueMessage(2)
self.msg_with_none = QueueMessage(None)
self.msg_unpackable = QueueMessage("abcde")
# these messages should be received
self.msg1_answer = QueueMessage(1)
self.msg2_answer = QueueMessage(2)
self.msg_with_none_answer = QueueMessage(None)
def test_in_port_capnp_optional(self):
"""Generate optional in port."""
in_port = InPort("index", Optional(int), None, 0)
capnp_in_port = dotdf_capnp.InPort.new_message()
in_port.capnp(capnp_in_port)
self.assertEqual(capnp_in_port.name, "index")
self.assertEqual(dill.loads(capnp_in_port.type), Int())
self.assertEqual(capnp_in_port.optional, True)
def test_in_port_capnp(self):
"""Generate in port."""
in_port = InPort("index", as_delta_type(int), None, 0)
capnp_in_port = dotdf_capnp.InPort.new_message()
in_port.capnp(capnp_in_port)
self.assertEqual(capnp_in_port.name, "index")
self.assertEqual(dill.loads(capnp_in_port.type), as_delta_type(int))
self.assertEqual(capnp_in_port.optional, False)
def test_neq_type_diff(self):
g1 = DeltaGraph()
n1 = RealNode(g1, [], OrderedDict([('a', int)]), OrderedDict())
in_p_1 = InPort('a', int, n1, 0)
g2 = DeltaGraph()
n2 = RealNode(g2, [], OrderedDict([('a', float)]), OrderedDict())
in_p_2 = InPort('a', float, n2, 0)
self.assertNotEqual(in_p_1, in_p_2)
def test_eq(self):
g1 = DeltaGraph()
n1 = RealNode(g1, [], OrderedDict([('a', int)]), OrderedDict())
in_p_1 = InPort('a', int, n1, 0)
self.assertEqual(in_p_1, in_p_1)
g2 = DeltaGraph()
n2 = RealNode(g2, [], OrderedDict([('a', int)]), OrderedDict())
in_p_2 = InPort('a', int, n2, 0)
self.assertEqual(in_p_1, in_p_2)
def test_in_port_capnp_wiring_direct(self):
"""In port has limit on port size."""
n = RealNode(DeltaGraph(), [], name='node_name')
in_port = InPort("index", as_delta_type(int), n, 1)
wire = dotdf_capnp.Wire.new_message()
nodes = [dotdf_capnp.Node.new_message()]
nodes[0].name = n.full_name
nodes[0].init("inPorts", 1)
nodes[0].inPorts[0].name = "index"
in_port.capnp_wiring(nodes, wire)
self.assertEqual(wire.destNode, 0)
self.assertEqual(wire.destInPort, 0)
self.assertEqual(wire.direct, True)
def test_in_port_capnp_wiring_direct(self):
"""In port has limit on port size."""
in_port = InPort(NamespacedName("node_name", "index"),
as_delta_type(int), None, 1)
wire = dotdf_capnp.Wire.new_message()
nodes = [dotdf_capnp.Node.new_message()]
nodes[0].name = "node_name"
nodes[0].init("inPorts", 1)
nodes[0].inPorts[0].name = "index"
in_port.capnp_wiring(nodes, wire)
self.assertEqual(wire.destNode, 0)
self.assertEqual(wire.destInPort, 0)
self.assertEqual(wire.direct, True)
def test_neq_dest_diff(self):
g1 = DeltaGraph()
n1 = RealNode(g1, [], OrderedDict(), OrderedDict([('out_a', int)]))
dest_n_1 = RealNode(g1, [], OrderedDict([('a', int)]), OrderedDict())
dest_1 = InPort('a', int, dest_n_1, 0)
out_p_1 = OutPort('out_a', int, dest_1, n1)
g2 = DeltaGraph()
n2 = RealNode(g2, [], OrderedDict(), OrderedDict([('out_a', int)]))
dest_n_2 = RealNode(g2, [], OrderedDict([('a', int)]), OrderedDict())
dest_2 = InPort('b', int, dest_n_2, 0)
out_p_2 = OutPort('out_a', int, dest_2, n2)
self.assertNotEqual(out_p_1, out_p_2)
def test_in_port_capnp_wiring(self):
"""Generate wiring."""
in_port = InPort(NamespacedName("node_name", "index"),
as_delta_type(int), None, 0)
wire = dotdf_capnp.Wire.new_message()
nodes = [dotdf_capnp.Node.new_message() for _ in range(3)]
nodes[0].name = "fake_name"
nodes[1].name = "fake_name"
nodes[2].name = "node_name"
nodes[2].init("inPorts", 3)
nodes[2].inPorts[0].name = "fake_name"
nodes[2].inPorts[1].name = "index"
nodes[2].inPorts[2].name = "fake_name"
in_port.capnp_wiring(nodes, wire)
self.assertEqual(wire.destNode, 2)
self.assertEqual(wire.destInPort, 1)
self.assertEqual(wire.direct, False)
def test_in_port_capnp_wiring(self):
"""Generate wiring."""
n = RealNode(DeltaGraph(), [], name='node_name')
in_port = InPort("index", as_delta_type(int), n, 0)
wire = dotdf_capnp.Wire.new_message()
nodes = [dotdf_capnp.Node.new_message() for _ in range(3)]
nodes[0].name = "fake_name"
nodes[1].name = "fake_name"
nodes[2].name = n.full_name
nodes[2].init("inPorts", 3)
nodes[2].inPorts[0].name = "fake_name"
nodes[2].inPorts[1].name = "index"
nodes[2].inPorts[2].name = "fake_name"
in_port.capnp_wiring(nodes, wire)
self.assertEqual(wire.destNode, 2)
self.assertEqual(wire.destInPort, 1)
self.assertEqual(wire.direct, False)
def test_DOptiona_of_DUnion(self):
port = InPort(NamespacedName("test_name", None),
DOptional(DUnion([DInt(), DFloat()])), None, 0)
self.assertEqual(port.port_type, DUnion([DInt(), DFloat()]))
self.assertEqual(port.is_optional, True)
def test_DUnion_of_single(self):
"""DUnion of a single type is not converted to a single type."""
port = InPort(NamespacedName("test_name", None), DUnion([DInt()]),
None, 0)
self.assertEqual(port.port_type, DUnion([DInt()]))
self.assertEqual(port.is_optional, False)
def test_DOptional(self):
port = InPort(NamespacedName("test_name", None), DOptional(DInt()),
None, 0)
self.assertEqual(port.port_type, DInt())
self.assertEqual(port.is_optional, True)
def test_non_Optional(self):
port = InPort(None, Int(), None, 0)
self.assertEqual(port.port_type, Int())
self.assertEqual(port.is_optional, False)
def test_Optional_of_Union(self):
port = InPort(None, Optional(Union([Int(), Float()])), None, 0)
self.assertEqual(port.port_type, Union([Int(), Float()]))
self.assertEqual(port.is_optional, True)
def test_Union(self):
port = InPort(None, Union([Int(), Float()]), None, 0)
self.assertEqual(port.port_type, Union([Int(), Float()]))
self.assertEqual(port.is_optional, False)
def test_Union_of_single(self):
"""Union of a single type is not converted to a single type."""
port = InPort(None, Union([Int()]), None, 0)
self.assertEqual(port.port_type, Union([Int()]))
self.assertEqual(port.is_optional, False)
def tb_deltaqueue_to_pa(pa):
def transfer_queue_to_pa(queue, pa):
"""Emulates the movement of data from the DeltaQueue to a PA
"""
if (yield pa.almost_full) != 1:
# write to the PA FIFO
yield
yield pa.wr_valid_in.eq(1)
yield pa.wr_data_in.eq(queue.get().msg)
yield
yield pa.wr_valid_in.eq(0)
yield
# First create a DeltaQueue object
# Hack: OutPort needs a "node" object with full_name attribute
mock_parent_node = SimpleNamespace()
mock_parent_node.full_name = "parent_node"
in_port = InPort("in", dl.Int(), None, self.tb_buf_width)
in_queue = DeltaQueue(OutPort("out", dl.Int(), in_port,
mock_parent_node),
maxsize=self.tb_buf_depth + 1)
# fill up the DeltaQueue so it has more items than the PA FIFO
data = []
for i in range(self.tb_buf_depth + 1):
# generate random entry
d = random.randint(0, pow(2, self.tb_buf_width))
data.append(d) # add entry to reference data for checking
in_queue.put(QueueMessage(d))
# check size of DeltaQueue
self.assertEqual(in_queue.qsize(), self.tb_buf_depth + 1)
# ensure PA is ready for consuming
yield
self.assertEqual((yield pa.rd_valid_out), 0)
self.assertEqual((yield pa.wr_ready_out), 1)
self.assertEqual((yield pa.rd_data_out), 0)
yield pa.rd_ready_in.eq(0)
# fill up the PA FIFO from the DeltaQueue until its full
for i in range(in_queue.qsize()):
yield from transfer_queue_to_pa(in_queue, pa)
# check PA FIFO is full
self.assertEqual((yield pa.fifo.dout), data[0])
self.assertEqual((yield pa.fifo.we), 0)
self.assertEqual((yield pa.almost_full), 1)
self.assertEqual((yield pa.num_fifo_elements), self.tb_buf_depth)
# check size of DeltaQueue
self.assertEqual(in_queue.qsize(), 1)
# read a single entry from the PA FIFO (the first entry)
yield pa.rd_ready_in.eq(1)
yield
self.assertEqual((yield pa.rd_valid_out), 1)
self.assertEqual((yield pa.rd_data_out), data[0])
yield pa.rd_ready_in.eq(0)
yield
data.pop(0) # remove first entry from reference data
# try and add remaining DeltaQueue data to the PA FIFO
for i in range(in_queue.qsize()):
if (yield pa.almost_full) != 1:
yield from transfer_queue_to_pa(in_queue, pa)
# check PA FIFO count hasn't changed
self.assertEqual((yield pa.almost_full), 1)
self.assertEqual((yield pa.num_fifo_elements), self.tb_buf_depth)
# check size of DeltaQueue
self.assertEqual(in_queue.qsize(), 0)
# check original first entry in PA FIFO is gone and all others remain
for d in data:
yield pa.rd_ready_in.eq(1)
yield
self.assertEqual((yield pa.rd_data_out), d)
yield pa.rd_ready_in.eq(0)
yield
def tb_pa_to_deltaqueue(pa):
def transfer_pa_to_queue(pa, queue):
"""Emulates the movement of data from the PA to a DeltaQueue
"""
if not queue.full():
# read a single entry from the PA FIFO (the first entry)
yield pa.rd_ready_in.eq(1)
yield
self.assertEqual((yield pa.rd_valid_out), 1)
# write to the queue
queue.put(QueueMessage((yield pa.rd_data_out)))
yield pa.rd_ready_in.eq(0)
yield
# First create a DeltaQueue object
# Hack: OutPort needs a "node" object with full_name attribute
mock_parent_node = SimpleNamespace()
mock_parent_node.full_name = "parent_node"
in_port = InPort("in", dl.Int(), None, self.tb_buf_width)
out_queue = DeltaQueue(OutPort("out", dl.Int(), in_port,
mock_parent_node),
maxsize=self.tb_buf_depth - 1)
yield
self.assertEqual((yield pa.rd_valid_out), 0)
self.assertEqual((yield pa.wr_ready_out), 1)
self.assertEqual((yield pa.rd_data_out), 0)
yield pa.rd_ready_in.eq(0)
# fill up PA FIFO so it has more items than max size of the DeltaQueue
data = []
for i in range(self.tb_buf_depth):
# generate random entry
d = random.randint(0, pow(2, self.tb_buf_width))
data.append(d) # add entry to reference data for checking
# write to the PA FIFO
yield
yield pa.wr_valid_in.eq(1)
yield pa.wr_data_in.eq(d)
yield
yield pa.wr_valid_in.eq(0)
yield
# check PA FIFO is full
self.assertEqual((yield pa.fifo.dout), data[0])
self.assertEqual((yield pa.fifo.we), 0)
self.assertEqual((yield pa.almost_full), 1)
self.assertEqual((yield pa.num_fifo_elements), self.tb_buf_depth)
# fill up the DeltaQueue from the PA FIFO until its full
for i in range(self.tb_buf_depth):
yield from transfer_pa_to_queue(pa, out_queue)
# check PA FIFO has been emptied except for 1
self.assertEqual((yield pa.almost_full), 0)
self.assertEqual((yield pa.num_fifo_elements), 1)
# check size of DeltaQueue
self.assertEqual(out_queue.qsize(), self.tb_buf_depth - 1)
# get a single item from the DeltaQueue
self.assertEqual(out_queue.get().msg, data[0])
data.pop(0) # remove first entry from reference data
# try and add remaining PA FIFO data to the DeltaQueue
for i in range((yield pa.num_fifo_elements)):
yield from transfer_pa_to_queue(pa, out_queue)
# check PA FIFO has been emptied
self.assertEqual((yield pa.almost_full), 0)
self.assertEqual((yield pa.num_fifo_elements), 0)
# check size of DeltaQueue
self.assertEqual(out_queue.qsize(), self.tb_buf_depth - 1)
# check the remaining data was moved into the DeltaQueue
for i in range(out_queue.qsize()):
self.assertEqual(out_queue.get().msg, data[i])
def test_Optional(self):
port = InPort(None, Optional(Int()), None, 0)
self.assertEqual(port.port_type, Int())
self.assertEqual(port.is_optional, True)