def rd_pc_imm8(va, value):
rd = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rd)
# pre-compute PC relative addr
oper1 = arm_dis.ArmImmOper(va+imm)
return oper0,oper1
def imm5_rn_rt(va, value):
imm = shmask(value, 6, 0x1f)
rn = shmask(value, 3, 0x7)
rt = shmask(value, 0, 0x7)
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmImmOffsetOper(rn, imm, va)
return oper0,oper1
def rd_sp_imm8(va, value):
rd = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rd)
# pre-compute PC relative addr
oper1 = arm_dis.ArmImmOffsetOper(arm_reg.REG_SP, imm)
return oper0,oper1
def rd_sp_imm8(va, value):
rd = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rd)
# pre-compute PC relative addr
oper1 = arm_dis.ArmImmOffsetOper(arm_reg.REG_SP, imm)
return oper0, oper1
def rm_rn_rt(va, value):
rt = shmask(value, 0, 0x7) # target
rn = shmask(value, 3, 0x7) # base
rm = shmask(value, 6, 0x7) # offset
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmRegOffsetOper(rn, rm, va)
return oper0,oper1
def rd_pc_imm8(va, value):
rd = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rd)
# pre-compute PC relative addr
oper1 = arm_dis.ArmImmOper(va + imm)
return oper0, oper1
def imm5_rn_rt(va, value):
imm = shmask(value, 6, 0x1f)
rn = shmask(value, 3, 0x7)
rt = shmask(value, 0, 0x7)
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmImmOffsetOper(rn, imm, va)
return oper0, oper1
def rm_rn_rt(va, value):
rt = shmask(value, 0, 0x7) # target
rn = shmask(value, 3, 0x7) # base
rm = shmask(value, 6, 0x7) # offset
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmRegOffsetOper(rn, rm, va)
return oper0, oper1
def ldmia(va, value):
rd = shmask(value, 8, 0x7)
reg_list = value & 0xff
oper0 = arm_dis.ArmRegOper(rd)
oper1 = arm_dis.ArmRegListOper(reg_list)
flags = 1<<11 # W flag indicating that write back should occur (marked by "!")
return oper0,oper1
def ldmia(va, value):
rd = shmask(value, 8, 0x7)
reg_list = value & 0xff
oper0 = arm_dis.ArmRegOper(rd)
oper1 = arm_dis.ArmRegListOper(reg_list)
flags = 1 << 11 # W flag indicating that write back should occur (marked by "!")
return oper0, oper1
def rt_pc_imm8(va, value):
rt = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmImmOffsetOper() # FIXME offset from PC
return oper0,oper1
def rm_reglist(va, value):
rm = shmask(value, 8, 0x7)
reglist = value & 0xff
oper0 = arm_dis.ArmRegOper(rm)
oper1 = arm_dis.ArmReglistOper(reglist)
return oper0,oper1
def sp_sp_imm7(va, value):
imm = shmask(value, 0, 0x7f)
o0 = arm_dis.ArmRegOper(arm_reg.REG_SP)
o1 = arm_dis.ArmRegOper(arm_reg.REG_SP)
o2 = arm_dis.ArmImmOper(imm*4)
return o0,o1,o2
def rt_pc_imm8(va, value):
rt = shmask(value, 8, 0x7)
imm = shmask(value, 0, 0xff)
oper0 = arm_dis.ArmRegOper(rt)
oper1 = arm_dis.ArmImmOffsetOper() # FIXME offset from PC
return oper0, oper1
def rm_reglist(va, value):
rm = shmask(value, 8, 0x7)
reglist = value & 0xff
oper0 = arm_dis.ArmRegOper(rm)
oper1 = arm_dis.ArmReglistOper(reglist)
return oper0, oper1
def sp_sp_imm7(va, value):
imm = shmask(value, 0, 0x7f)
o0 = arm_dis.ArmRegOper(arm_reg.REG_SP)
o1 = arm_dis.ArmRegOper(arm_reg.REG_SP)
o2 = arm_dis.ArmImmOper(imm * 4)
return o0, o1, o2
