def execute_bcond(s, inst): """ B<COND>: IF (Passed)<COND>)) then PC = PC + (SignExtend(SIMM) << 1) BL: LR = next PC; PC = PC + (SignExtend(SIMM) << 1) """ if is16bit: inst.bits &= 0xFFFF cond = inst.cond imm = inst.bcond_imm if cond == 0 and imm == 0: raise RuntimeError( ( "Epiphany simulator caught infinite loop at runtime. " + "Instruction at pc=%s is attempting to " + "branch unconditionally to itself." ) % hex(s.pc) ) if cond == 0b1111: # Branch and link (BL). s.rf[epiphany.isa.reg_map["LR"]] = s.pc + (2 if is16bit else 4) if condition_passed(s, cond): offset = (signed(sext_8(imm)) << 1) if is16bit else (signed(sext_24(imm)) << 1) s.pc = trim_32(s.pc + offset) else: s.pc += 2 if is16bit else 4 s.debug_flags()
def test_sign_extend_24bit(): assert sext_24(0b011111111111111111111111) == 0b011111111111111111111111 assert sext_24(0b111111111111111111111111) == 0xFFFFFFFF