def test_end2end_tfc_w1a2_verify_dataflow_part():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_ipstitch.onnx")
x = np.zeros((1, 784), dtype=np.float32)
inp_name = model.graph.input[0].name
out_name = model.graph.output[0].name
inp_dict = {inp_name: x}
# npysim
model = model.transform(CodeGen_npysim())
model = model.transform(Compile())
model = model.transform(SetExecMode("npysim"))
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_npysim.onnx")
ret_npysim = execute_onnx(model, inp_dict, True)
res_npysim = ret_npysim[out_name]
# node-by-node rtlsim
model = model.transform(SetExecMode("rtlsim"))
getCustomOp(model.graph.node[0]).set_nodeattr("rtlsim_trace", "default")
getCustomOp(model.graph.node[1]).set_nodeattr("rtlsim_trace", "default")
getCustomOp(model.graph.node[2]).set_nodeattr("rtlsim_trace", "default")
getCustomOp(model.graph.node[3]).set_nodeattr("rtlsim_trace", "default")
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_nodebynode_rtlsim.onnx")
ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
# whole-network (ip-stitched) rtlsim
model.set_metadata_prop("exec_mode", "rtlsim")
model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_whole_rtlsim.onnx")
ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
res_rtlsim_whole = ret_rtlsim_whole[out_name]
assert np.isclose(res_npysim, res_rtlsim_nodebynode).all()
assert np.isclose(res_npysim, res_rtlsim_whole).all()
def test_end2end_tfc_w1a2_verify_dataflow_part():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_ipstitch.onnx")
x = np.zeros((1, 784), dtype=np.float32)
inp_name = model.graph.input[0].name
out_name = model.graph.output[0].name
inp_dict = {inp_name: x}
# cppsim
model = model.transform(PrepareCppSim())
model = model.transform(CompileCppSim())
model = model.transform(SetExecMode("cppsim"))
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_cppsim.onnx")
ret_cppsim = execute_onnx(model, inp_dict, True)
res_cppsim = ret_cppsim[out_name]
# node-by-node rtlsim
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(PrepareRTLSim())
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_nodebynode_rtlsim.onnx")
ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
# whole-network (ip-stitched) rtlsim
model.set_metadata_prop("exec_mode", "rtlsim")
model.save(build_dir + "/end2end_tfc_w1a2_ipstitch_whole_rtlsim.onnx")
ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
res_rtlsim_whole = ret_rtlsim_whole[out_name]
assert np.isclose(res_cppsim, res_rtlsim_nodebynode).all()
assert np.isclose(res_cppsim, res_rtlsim_whole).all()
def test_end2end_cnv_w1a1_verify_dataflow_part():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_ipstitch.onnx")
x = np.zeros((1, 32, 32, 3), dtype=np.float32)
inp_name = model.graph.input[0].name
out_name = model.graph.output[0].name
inp_dict = {inp_name: x}
# cppsim
model = model.transform(PrepareCppSim())
model = model.transform(CompileCppSim())
model = model.transform(SetExecMode("cppsim"))
model.save(build_dir + "/end2end_cnv_w1a1_ipgen_cppsim.onnx")
ret_cppsim = execute_onnx(model, inp_dict, True)
res_cppsim = ret_cppsim[out_name]
# node-by-node rtlsim
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(PrepareRTLSim())
model.save(build_dir + "/end2end_cnv_w1a1_ipgen_nodebynode_rtlsim.onnx")
ret_rtlsim_nodebynode = execute_onnx(model, inp_dict, True)
res_rtlsim_nodebynode = ret_rtlsim_nodebynode[out_name]
# whole-network (ip-stitched) rtlsim
model.set_metadata_prop("exec_mode", "rtlsim")
model.save(build_dir + "/end2end_cnv_w1a1_ipstitch_whole_rtlsim.onnx")
# this is a particularly long-running test, set liveness thr. to unlimited
os.environ["LIVENESS_THRESHOLD"] = "-1"
ret_rtlsim_whole = execute_onnx(model, inp_dict, True)
res_rtlsim_whole = ret_rtlsim_whole[out_name]
assert np.isclose(res_cppsim, res_rtlsim_nodebynode).all()
assert np.isclose(res_cppsim, res_rtlsim_whole).all()
def apply(self, model):
_check_vitis_envvars()
# first infer layouts
model = model.transform(InferDataLayouts())
# prepare at global level, then break up into kernels
prep_transforms = [
MakePYNQDriver(platform="alveo"),
InsertIODMA(512),
InsertDWC(),
]
for trn in prep_transforms:
model = model.transform(trn)
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
model = model.transform(Floorplan(floorplan=self.floorplan_file))
model = model.transform(CreateDataflowPartition())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
# Build each kernel individually
sdp_nodes = model.get_nodes_by_op_type("StreamingDataflowPartition")
for sdp_node in sdp_nodes:
sdp_node = getCustomOp(sdp_node)
dataflow_model_filename = sdp_node.get_nodeattr("model")
kernel_model = ModelWrapper(dataflow_model_filename)
kernel_model = kernel_model.transform(InsertFIFO())
kernel_model = kernel_model.transform(
InsertTLastMarker(both=True, external=False, dynamic=False))
kernel_model = kernel_model.transform(GiveUniqueNodeNames())
kernel_model.save(dataflow_model_filename)
kernel_model = kernel_model.transform(
PrepareIP(self.fpga_part, self.period_ns))
kernel_model = kernel_model.transform(HLSSynthIP())
kernel_model = kernel_model.transform(
CreateStitchedIP(self.fpga_part, self.period_ns,
sdp_node.onnx_node.name, True))
kernel_model = kernel_model.transform(
CreateVitisXO(sdp_node.onnx_node.name))
kernel_model.set_metadata_prop("platform", "alveo")
kernel_model.save(dataflow_model_filename)
# Assemble design from kernels
model = model.transform(
VitisLink(
self.platform,
round(1000 / self.period_ns),
strategy=self.strategy,
enable_debug=self.enable_debug,
))
# set platform attribute for correct remote execution
model.set_metadata_prop("platform", "alveo")
return (model, False)
def test_fpgadataflow_ipstitch_gen_model(): # exec_mode):
model = create_one_fc_model()
if model.graph.node[0].op_type == "StreamingDataflowPartition":
sdp_node = getCustomOp(model.graph.node[0])
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = ModelWrapper(sdp_node.get_nodeattr("model"))
model.set_metadata_prop("exec_mode", "remote_pynq")
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(CodeGen_ipgen(test_fpga_part, 5))
model = model.transform(HLSSynth_IPGen())
assert model.graph.node[0].op_type == "StreamingFCLayer_Batch"
assert model.graph.node[-1].op_type == "TLastMarker"
model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx")
def test_fpgadataflow_ipstitch_rtlsim():
model = ModelWrapper(ip_stitch_model_dir +
"/test_fpgadataflow_ip_stitch.onnx")
model.set_metadata_prop("rtlsim_trace", "whole_trace.vcd")
sim = pyverilate_stitched_ip(model)
exp_io = [
"ap_clk_0",
"ap_rst_n_0",
"in0_V_V_0_tdata",
"in0_V_V_0_tready",
"in0_V_V_0_tvalid",
"out_r_0_tdata",
"out_r_0_tkeep",
"out_r_0_tlast",
"out_r_0_tready",
"out_r_0_tvalid",
"s_axi_control_0_araddr",
"s_axi_control_0_arready",
"s_axi_control_0_arvalid",
"s_axi_control_0_awaddr",
"s_axi_control_0_awready",
"s_axi_control_0_awvalid",
"s_axi_control_0_bready",
"s_axi_control_0_bresp",
"s_axi_control_0_bvalid",
"s_axi_control_0_rdata",
"s_axi_control_0_rready",
"s_axi_control_0_rresp",
"s_axi_control_0_rvalid",
"s_axi_control_0_wdata",
"s_axi_control_0_wready",
"s_axi_control_0_wstrb",
"s_axi_control_0_wvalid",
]
assert dir(sim.io) == exp_io
model.set_metadata_prop("exec_mode", "rtlsim")
idt = model.get_tensor_datatype("inp")
ishape = model.get_tensor_shape("inp")
x = gen_finn_dt_tensor(idt, ishape)
# x = np.zeros(ishape, dtype=np.float32)
# x = np.asarray([[-2, -1, 0, 1]], dtype=np.float32)
rtlsim_res = execute_onnx(model, {"inp": x})["outp"]
assert (rtlsim_res == x).all()
def apply(self, model):
# first infer layouts
model = model.transform(InferDataLayouts())
# prepare at global level, then break up into kernels
prep_transforms = [
InsertIODMA(64),
InsertDWC(),
Floorplan(),
CreateDataflowPartition(),
]
for trn in prep_transforms:
model = model.transform(trn)
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
# Build each kernel individually
sdp_nodes = model.get_nodes_by_op_type("StreamingDataflowPartition")
for sdp_node in sdp_nodes:
prefix = sdp_node.name + "_"
sdp_node = getCustomOp(sdp_node)
dataflow_model_filename = sdp_node.get_nodeattr("model")
kernel_model = ModelWrapper(dataflow_model_filename)
kernel_model = kernel_model.transform(InsertFIFO())
kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix))
kernel_model.save(dataflow_model_filename)
kernel_model = kernel_model.transform(
PrepareIP(self.fpga_part, self.period_ns))
kernel_model = kernel_model.transform(HLSSynthIP())
kernel_model = kernel_model.transform(
CreateStitchedIP(self.fpga_part, self.period_ns,
sdp_node.onnx_node.name, True))
kernel_model.set_metadata_prop("platform", "zynq-iodma")
kernel_model.save(dataflow_model_filename)
# Assemble design from IPs
model = model.transform(
MakeZYNQProject(self.platform, enable_debug=self.enable_debug))
# set platform attribute for correct remote execution
model.set_metadata_prop("platform", "zynq-iodma")
# create driver
model = model.transform(MakePYNQDriver(platform="zynq-iodma"))
return (model, False)
def test_fpgadataflow_ipstitch_rtlsim():
model = ModelWrapper(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch.onnx")
sim = pyverilate_stitched_ip(model)
exp_io = [
"ap_clk_0",
"ap_rst_n_0",
"in0_V_V_0_tdata",
"in0_V_V_0_tready",
"in0_V_V_0_tvalid",
"out_r_0_tdata",
"out_r_0_tkeep",
"out_r_0_tlast",
"out_r_0_tready",
"out_r_0_tvalid",
]
assert dir(sim.io) == exp_io
model.set_metadata_prop("exec_mode", "rtlsim")
idt = model.get_tensor_datatype("inp")
ishape = model.get_tensor_shape("inp")
x = gen_finn_dt_tensor(idt, ishape)
rtlsim_res = execute_onnx(model, {"inp": x})["outp"]
assert (rtlsim_res == x).all()
