def step_out_of_context_synthesis(model: ModelWrapper, cfg: DataflowBuildConfig):
"""Run out-of-context synthesis and generate reports.
Depends on the DataflowOutputType.STITCHED_IP output product."""
if DataflowOutputType.OOC_SYNTH in cfg.generate_outputs:
assert (
DataflowOutputType.STITCHED_IP in cfg.generate_outputs
), "OOC needs stitched IP"
model = model.transform(
SynthOutOfContext(
part=cfg._resolve_fpga_part(), clk_period_ns=cfg.synth_clk_period_ns
)
)
report_dir = cfg.output_dir + "/report"
os.makedirs(report_dir, exist_ok=True)
ooc_res_dict = model.get_metadata_prop("res_total_ooc_synth")
ooc_res_dict = eval(ooc_res_dict)
estimate_network_performance = model.analysis(dataflow_performance)
# add some more metrics to estimated performance
n_clock_cycles_per_sec = float(ooc_res_dict["fmax_mhz"]) * (10 ** 6)
est_fps = n_clock_cycles_per_sec / estimate_network_performance["max_cycles"]
ooc_res_dict["estimated_throughput_fps"] = est_fps
with open(report_dir + "/ooc_synth_and_timing.json", "w") as f:
json.dump(ooc_res_dict, f, indent=2)
return model
def test_fpgadataflow_ipstitch_synth_ooc(mem_mode):
model = load_test_checkpoint_or_skip(
ip_stitch_model_dir +
"/test_fpgadataflow_ip_stitch_%s.onnx" % mem_mode)
model = model.transform(SynthOutOfContext(test_fpga_part, 5))
ret = model.get_metadata_prop("res_total_ooc_synth")
assert ret is not None
# example expected output: (details may differ based on Vivado version etc)
# "{'vivado_proj_folder': ...,
# 'LUT': 708.0, 'FF': 1516.0, 'DSP': 0.0, 'BRAM': 0.0, 'WNS': 0.152, '': 0,
# 'fmax_mhz': 206.27062706270627}"
ret = eval(ret)
assert ret["LUT"] > 0
assert ret["FF"] > 0
assert ret["DSP"] == 0
assert ret["BRAM"] == 0
assert ret["fmax_mhz"] > 100