def setUpClass(TestUploadToFPGA):
"""Loads a small set of values into memory, of all 5 different types."""
regmem = [1,6,8,4] + [0]*12
prgmem = [18,24,0,5] + [0]*508
hskmem = [0,1,2,3] + [0]*508
seqmem = [1,2] + [0]*1022
clvmem = [3,4] + [0]*126
fpga.upload_to_fpga(REG_MEM=regmem, SEQ_MEM=seqmem, PRG_MEM=prgmem,
HSK_SEL_MEM=hskmem,VOLT_MEM=clvmem)
def setUp(self):
"""Loads a small set of values into memory, of 3 different types"""
regmem = [1,6,8,4]
seqmem = []
prgmem = [18,24,0,5]
hskmem = [0,1,2,3]
voltmem = []
fpga.upload_to_fpga(REG_MEM=regmem, SEQ_MEM=seqmem,
PRG_MEM=prgmem,HSK_SEL_MEM=hskmem,
VOLT_MEM=voltmem)
def setUpClass(TestUploadToFPGA):
"""Loads a small set of values into memory, of all 5 different types."""
regmem = [1, 6, 8, 4] + [0] * 12
prgmem = [18, 24, 0, 5] + [0] * 508
hskmem = [0, 1, 2, 3] + [0] * 508
seqmem = [1, 2] + [0] * 1022
clvmem = [3, 4] + [0] * 126
fpga.upload_to_fpga(REG_MEM=regmem,
SEQ_MEM=seqmem,
PRG_MEM=prgmem,
HSK_SEL_MEM=hskmem,
VOLT_MEM=clvmem)
def test_update(self):
"""Tests that if a new array is input, the file is changed
(and no other files are altered)."""
clvmem = [19, 27] + [0] * 126
fpga.upload_to_fpga(VOLT_MEM=clvmem)
self.assertEqual([1245211] + [0] * 63, self.get_32bit('CLVMem.bin'))
clvmem = [0] * 128
fpga.upload_to_fpga(VOLT_MEM=clvmem)
self.assertEqual([0] * 64, self.get_32bit('CLVMem.bin'))
self.assertEqual([65542, 524292] + [0] * 6,
self.get_32bit('RegMem.bin'))
self.assertEqual([0, 1, 0, 2] + [0] * 2044,
self.get_32bit('SeqMem.bin'))
self.assertEqual([0, 18, 0, 24, 0, 0, 0, 5] + [0] * 1016,
self.get_32bit('PrgMem.bin'))
self.assertEqual([66051] + [0] * 127, self.get_32bit('HSKMem.bin'))
def test_update(self):
"""Tests that if a new array is input, the file is changed
(and no other files are altered)."""
clvmem = [19,27] + [0]*126
fpga.upload_to_fpga(VOLT_MEM=clvmem)
self.assertEqual([1245211]+[0]*63,
self.get_32bit('CLVMem.bin'))
clvmem = [0]*128
fpga.upload_to_fpga(VOLT_MEM=clvmem)
self.assertEqual([0]*64,
self.get_32bit('CLVMem.bin'))
self.assertEqual([65542,524292]+[0]*6,
self.get_32bit('RegMem.bin'))
self.assertEqual([0,1,0,2]+[0]*2044,
self.get_32bit('SeqMem.bin'))
self.assertEqual([0,18,0,24,0,0,0,5]+[0]*1016,
self.get_32bit('PrgMem.bin'))
self.assertEqual([66051]+[0]*127,
self.get_32bit('HSKMem.bin'))
