コード例 #1
0
ファイル: __init__.py プロジェクト: zhufengGNSS/fpga-sdrlib
def make_twiddlefactors(pck, fn, dependencies, extraargs={}):
    # dependencies is not used
    fft_length = extraargs.get('N', None)
    width = extraargs.get('width', None)
    if fft_length is None:
        raise ValueError("N for twiddlefactors.v is not known.")
    if width is None:
        raise ValueError("width for twidlefactors.v is not known.")
    vs = [
        cmath.exp(-i * 2j * cmath.pi / fft_length)
        for i in range(0, fft_length / 2)
    ]
    tfs = cs_to_dicts(vs, width, clean1=False)
    tf_dict = {
        'N': fft_length,
        'log_N': logceil(fft_length),
        'width': width,
        'tfs': tfs,
    }
    assert (fn == 'twiddlefactors.v.t')
    twiddlefactors_fn = 'twiddlefactors_{0}.v'.format(fft_length)
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, twiddlefactors_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    format_template(in_fn, out_fn, tf_dict)
    return out_fn, {}
コード例 #2
0
ファイル: __init__.py プロジェクト: benreynwar/fpga-sdrlib
def make_twiddlefactors(pck, fn, dependencies, extraargs={}):
    # dependencies is not used
    fft_length = extraargs.get('N', None)
    width = extraargs.get('width', None)
    if fft_length is None:
        raise ValueError("N for twiddlefactors.v is not known.")
    if width is None:
        raise ValueError("width for twidlefactors.v is not known.")
    vs = [cmath.exp(-i*2j*cmath.pi/fft_length) for i in range(0, fft_length/2)]
    tfs = cs_to_dicts(vs, width, clean1=False)
    tf_dict = {
        'N': fft_length,
        'log_N': logceil(fft_length),
        'width': width,
        'tfs': tfs,
        }
    assert(fn == 'twiddlefactors.v.t')
    twiddlefactors_fn = 'twiddlefactors_{0}.v'.format(fft_length)
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, twiddlefactors_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    format_template(in_fn, out_fn, 
                    tf_dict)
    return out_fn, {}
コード例 #3
0
ファイル: __init__.py プロジェクト: zhufengGNSS/fpga-sdrlib
def fft_length_template(pck, fn, dependencies, extraargs={}):
    fft_length = extraargs.get('N', None)
    if fft_length is None:
        raise ValueError("N for stage_to_stage.v is not known.")
    template_dict = {'N': fft_length}
    assert (fn[-4:] == '.v.t')
    ss_fn = fn[:-4] + "_" + str(fft_length) + '.v'
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, ss_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    format_template(in_fn, out_fn, template_dict)
    out_extraargs = {}
    for d in dependencies:
        out_extraargs[d] = extraargs
    return out_fn, out_extraargs
コード例 #4
0
ファイル: __init__.py プロジェクト: benreynwar/fpga-sdrlib
def fft_length_template(pck, fn, dependencies, extraargs={}):
    fft_length = extraargs.get('N', None)
    if fft_length is None:
        raise ValueError("N for stage_to_stage.v is not known.")
    template_dict = {'N': fft_length}
    assert(fn[-4:] == '.v.t')
    ss_fn = fn[:-4] + "_" + str(fft_length) + '.v'
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, ss_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    format_template(in_fn, out_fn, 
                    template_dict)
    out_extraargs = {}
    for d in dependencies:
        out_extraargs[d] = extraargs
    return out_fn, out_extraargs
コード例 #5
0
ファイル: __init__.py プロジェクト: benreynwar/fpga-sdrlib
def make_summult(pck, fn, dependencies, extraargs={}):
    # dependencies is not used
    length = extraargs.get('summult_length', None)
    if length is None:
        raise ValueError("Length for summult.v is not known.")
    log_length = int(math.ceil(math.log(length)/math.log(2)))
    # Generate summult file
    assert(fn == 'summult.v.t')
    summult_fn = 'summult_{0}.v'.format(length)
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, summult_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    real_sum = ["x_re_y[{0}]".format(i) for i in range(length)]
    real_sum = " + ".join(real_sum)
    imag_sum = ["x_im_y[{0}]".format(i) for i in range(length)]
    imag_sum = " + ".join(imag_sum)
    format_template(in_fn, out_fn, 
                    {'real_sum': real_sum,
                     'imag_sum': imag_sum})
    return out_fn, {}
コード例 #6
0
ファイル: __init__.py プロジェクト: benreynwar/fpga-sdrlib
def make_filter(pck, fn, dependencies, extraargs={}):
    """
    Generate filter_X.v from filter.v
    
    This is done so that we can convert the 2D array tapvalues to
    a 1D array to pass to summult.
    """
    # dependencies is not used
    length = extraargs.get('summult_length', None)
    if length is None:
        raise ValueError("Length for filter.v is not known.")
    log_length = int(math.ceil(math.log(length)/math.log(2)))
    # Generate filter file
    assert(fn == 'filter.v.t')
    summult_fn = 'filter_{0}.v'.format(length)
    in_fn = os.path.join(config.verilogdir, pck, fn)
    out_fn = os.path.join(config.builddir, pck, summult_fn)
    out_dir = os.path.join(config.builddir, pck)
    if not os.path.exists(out_dir):
        os.makedirs(out_dir)
    tapvalues_1D = ["tapvalues[{0}]".format(i) for i in reversed(range(length))]
    tapvalues_1D = "{" + ", ".join(tapvalues_1D) + "}"
    format_template(in_fn, out_fn, {'tapvalues_1D': tapvalues_1D})
    return out_fn, {'summult.v.t': extraargs}