def test_parse(self):
spec = ControllerSpec(8, 8)
message = int('10101100110011110000', 2)
parsed_opcode = spec.parse_opcode(message)
self.assertEquals(parsed_opcode, int('1010', 2))
parsed_addr = spec.parse_addr(message)
self.assertEquals(parsed_addr, int('11001100', 2))
parsed_data = spec.parse_data(message)
self.assertEquals(parsed_data, int('11110000', 2))
parsed_value = spec.parse_value(message)
self.assertEquals(parsed_value, int('1100110011110000', 2))
def test_parse(self):
spec = ControllerSpec(8, 8)
message = int('10101100110011110000', 2)
parsed_opcode = spec.parse_opcode(message)
self.assertEquals(parsed_opcode, int('1010', 2))
parsed_addr = spec.parse_addr(message)
self.assertEquals(parsed_addr, int('11001100', 2))
parsed_data = spec.parse_data(message)
self.assertEquals(parsed_data, int('11110000', 2))
parsed_value = spec.parse_value(message)
self.assertEquals(parsed_value, int('1100110011110000', 2))
class ControllerTestCase(TestCase):
HALF_PERIOD = 5
WIDTH_ADDR = 32
WIDTH_DATA = 8
MEM_INIT = {3: 4, 4: 5, 5: 6}
EXP_RESET_ACTIVE = False
def setUp(self):
self.spec = ControllerSpec(width_addr=self.WIDTH_ADDR,
width_data=self.WIDTH_DATA)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.rx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.rx_ready = Signal(False)
self.tx_ready = Signal(True)
self.exp_data_read = Signal(intbv(0)[self.spec.width_data:0])
# Output signals
self.rx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.tx_next = Signal(False)
self.exp_addr = Signal(intbv(0)[self.spec.width_addr:0])
self.exp_data_write = Signal(intbv(0)[self.spec.width_data:0])
self.exp_wen = Signal(False)
self.exp_reset = ResetSignal(not self.EXP_RESET_ACTIVE,
active=self.EXP_RESET_ACTIVE,
async=False)
self.exp_clk_en = Signal(False)
self.clockgen = ClockGen(clk=self.clk, half_period=self.HALF_PERIOD)
self.controller = Controller(spec=self.spec,
clk=self.clk,
reset=self.reset,
rx_msg=self.rx_msg,
rx_next=self.rx_next,
rx_ready=self.rx_ready,
tx_msg=self.tx_msg,
tx_next=self.tx_next,
tx_ready=self.tx_ready,
exp_addr=self.exp_addr,
exp_data_write=self.exp_data_write,
exp_data_read=self.exp_data_read,
exp_wen=self.exp_wen,
exp_reset=self.exp_reset,
exp_clk_en=self.exp_clk_en,
exp_reset_active=self.EXP_RESET_ACTIVE)
self.mock_experiment = MockExperimentSetup(
self.clk, self.reset, self.exp_addr, self.exp_data_write,
self.exp_data_read, self.exp_wen, self.exp_reset, self.exp_clk_en,
self.MEM_INIT)
def simulate(self, test_logic, duration=None):
sim = Simulation(self.clockgen, self.controller, self.mock_experiment,
*test_logic)
sim.run(duration, quiet=False)
def stop_simulation(self):
raise StopSimulation()
def assert_value_type_response(self, opcode_expected, value_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg)
value_actual = self.spec.parse_value(self.tx_msg)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(value_actual, value_expected)
def assert_addr_type_response(self, opcode_expected, address_expected,
data_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg)
addr_actual = self.spec.parse_addr(self.tx_msg)
data_actual = self.spec.parse_data(self.tx_msg)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(addr_actual, addr_expected)
self.assertEquals(data_actual, data_expected)
def test_reset(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.assertFalse(self.rx_next)
self.assertFalse(self.tx_next)
self.assertEquals(self.exp_reset, self.EXP_RESET_ACTIVE)
self.assertFalse(self.exp_wen)
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
self.assertFalse(self.exp_clk_en)
self.stop_simulation()
self.simulate([test])
def test_cmd_read(self):
opcode = self.spec.opcode_cmd_read
cmd1 = self.spec.addr_type_message(opcode, 3, 0)
cmd2 = self.spec.addr_type_message(opcode, 4, 0)
expected1 = self.spec.addr_type_message(
self.spec.opcode_res_read_success, 3, 4)
expected2 = self.spec.addr_type_message(
self.spec.opcode_res_read_success, 4, 5)
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.rx_msg.next = cmd1
self.rx_ready.next = True
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
yield self.clk.negedge
self.assertEquals(self.tx_msg, expected1)
self.assertTrue(self.tx_next)
self.rx_msg.next = cmd2
self.rx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
yield self.clk.negedge
self.assertEquals(self.tx_msg, expected2)
self.assertTrue(self.tx_next)
self.rx_ready.next = False
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.stop_simulation()
self.simulate([test])
def test_cmd_write(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = True
self.rx_msg.next = self.spec.addr_type_message(
self.spec.opcode_cmd_write, 88, 9)
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
self.assertTrue(self.exp_wen)
self.assertEquals(self.exp_addr, 88)
yield self.clk.negedge
self.assertEquals(self.exp_data_read, 9)
self.assertTrue(self.tx_next)
self.assertEquals(self.exp_addr, 88)
self.rx_ready.next = False
yield delay(1)
self.assertFalse(self.rx_next)
self.assertFalse(self.exp_wen)
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.stop_simulation()
self.simulate([test])
def test_cmd_reset(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
yield self.clk.negedge
self.assertEquals(self.exp_reset, not self.EXP_RESET_ACTIVE)
self.rx_msg.next = self.spec.value_type_message(
self.spec.opcode_cmd_reset, 0)
self.rx_ready.next = True
self.tx_ready.next = True
yield delay(1)
self.assertEquals(self.exp_reset, self.EXP_RESET_ACTIVE)
yield self.clk.negedge
self.assertEquals(
self.tx_msg,
self.spec.value_type_message(
self.spec.opcode_res_reset_success, 0))
self.stop_simulation()
self.simulate([test])
def test_cmd_step(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = False
self.tx_ready.next = True
yield self.clk.posedge
yield delay(1)
self.assertFalse(self.exp_clk_en)
self.rx_msg.next = self.spec.value_type_message(
self.spec.opcode_cmd_step, 0)
self.rx_ready.next = True
yield delay(1)
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
yield delay(1)
self.assertTrue(self.exp_clk_en)
self.assertFalse(self.tx_next)
yield self.clk.posedge
yield delay(1)
self.assertTrue(self.exp_clk_en)
self.assertTrue(self.tx_next)
self.rx_ready.next = False
yield self.clk.negedge
yield delay(1)
self.assertFalse(self.exp_clk_en)
self.stop_simulation()
self.simulate([test])
def test_cmd_start_pause(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = False
self.tx_ready.next = True
self.stop_simulation()
self.simulate([test])
class ControllerResponseComposeTestCase(TestCase):
WIDTH_ADDR = 32
WIDTH_DATA = 8
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
#input signals
self.opcode_res = Signal(intbv(0)[self.spec.width_opcode:0])
self.addr = Signal(intbv(0)[self.spec.width_addr:0])
self.data = Signal(intbv(0)[self.spec.width_data:0])
self.nop = Signal(False)
self.tx_ready = Signal(False)
self.cycle_count = Signal(intbv(0)[self.spec.width_value:0])
# Output signals
self.tx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.response_compose = ControllerResponseCompose(spec=self.spec,
opcode_res=self.opcode_res, addr=self.addr, data=self.data,
nop=self.nop, cycle_count=self.cycle_count,
tx_ready=self.tx_ready, tx_next=self.tx_next,
tx_msg=self.tx_msg)
def simulate(self, test_logic, duration=None):
sim = Simulation(self.response_compose, test_logic)
sim.run(duration, quiet=False)
def stop_simulation(self):
raise StopSimulation()
def assert_value_type_response(self, opcode_expected, value_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg.val)
value_actual = self.spec.parse_value(self.tx_msg.val)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(value_actual, value_expected)
def assert_addr_type_response(self, opcode_expected, addr_expected,
data_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg.val)
addr_actual = self.spec.parse_addr(self.tx_msg.val)
data_actual = self.spec.parse_data(self.tx_msg.val)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(addr_actual, addr_expected)
self.assertEquals(data_actual, data_expected)
def test_tx_next(self):
@instance
def test():
yield delay(1)
self.nop.next = True
self.tx_ready.next = False
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = True
self.tx_ready.next = True
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = False
self.tx_ready.next = False
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = False
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.tx_next)
self.stop_simulation()
self.simulate(test)
def test_tx_msg(self):
@instance
def test():
self.nop.next = False
self.tx_ready.next = True
# read success
self.addr.next = 23
self.data.next = 3
self.opcode_res.next = self.spec.opcode_res_read_success
yield delay(10)
self.assert_addr_type_response(self.spec.opcode_res_read_success,
23, 3)
# read error
self.opcode_res.next = self.spec.opcode_res_read_error_mode
yield delay(1)
self.assert_addr_type_response(
self.spec.opcode_res_read_error_mode, 23, 0)
# write success
self.addr.next = 26
self.data.next = 6
self.opcode_res.next = self.spec.opcode_res_write_success
yield delay(10)
self.assert_addr_type_response(self.spec.opcode_res_write_success,
26, 6)
# read error
self.opcode_res.next = self.spec.opcode_res_write_error_mode
yield delay(1)
self.assert_addr_type_response(
self.spec.opcode_res_write_error_mode, 26, 0)
# reset success
self.opcode_res.next = self.spec.opcode_res_reset_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_reset_success, 0)
# Step success
self.cycle_count.next = 34523
self.opcode_res.next = self.spec.opcode_res_step_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_step_success, 34524)
# Step error
self.opcode_res.next = self.spec.opcode_res_step_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_step_error_mode, 0)
# Start success
self.cycle_count.next = 3523
self.opcode_res.next = self.spec.opcode_res_start_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_start_success, 3523)
# Start error
self.opcode_res.next = self.spec.opcode_res_start_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_start_error_mode, 0)
# Pause success
self.cycle_count.next = 823
self.opcode_res.next = self.spec.opcode_res_pause_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_pause_success, 823)
# Pause error
self.opcode_res.next = self.spec.opcode_res_pause_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_pause_error_mode, 0)
# Status
self.cycle_count.next = 11823
self.opcode_res.next = self.spec.opcode_res_status
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_status, 11823)
self.stop_simulation()
self.simulate(test)