def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire(['a', 'b', 'c', 's', 'r', 'q', 'qb', 'o']))
dut0 = NMOS_NMAJ(
"nmos_maj_0_u",
dict([('OUT', self.netlist['o']), ('I0', self.netlist['a']),
('I1', self.netlist['b']), ('I2', self.netlist['c'])]), self)
self.gatelist = [dut0]
self.pi_events = []
vector_string = '''
PI a
PI b
PI c
PO o
# abc o
# ---------
000 H
001 H
010 H
011 L
100 H
101 L
110 L
111 L
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self,options)
self.netlist.update( gate.wire([ 'in0', 'in1', 'out', 'n0']))
self.netlist['out'].pullup_str=1
dut0 = UNMOS( "unmos_0_u", [ self.netlist['n0'], self.netlist['vss'], self.netlist['in0']], self)
dut1 = UNMOS( "unmos_1_u", [ self.netlist['out'], self.netlist['n0'], self.netlist['in1']], self)
self.gatelist = [dut0, dut1]
vector_string = '''
PI in0
PI in1
PO out
# ii o
# nn u
# 01 t
# ------
00 H
01 H
10 H
11 L
01 H
10 H
00 H
10 H
11 L
'''
self.events = self.read_flex_string( vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'clk', 'in0', 'in1', 'in2', 'net0', 'net1', 'out1', 'out2',
'rstb'
]))
dut0 = NMOS_NMAJ(
"maj_0_u",
dict([('OUT', self.netlist['net0']), ('I0', self.netlist['in1']),
('I1', self.netlist['in2']), ('I2', self.netlist['in0'])]),
self)
dut1 = NMOS_XOR2(
"xor_1_u",
dict([('OUT', self.netlist['net1']), ('I0', self.netlist['out1']),
('I1', self.netlist['in1'])]), self)
dut2 = NMOS_XOR2(
"xor_2_u",
dict([('OUT', self.netlist['out1']), ('I0', self.netlist['in2']),
('I1', self.netlist['in1'])]), self)
dut3 = NMOS_DFF(
"dff_0_u",
dict([('Q', self.netlist['out2']), ('RSTB', self.netlist['rstb']),
('PHI', self.netlist['clk']), ('D', self.netlist['net1'])]),
self)
self.gatelist = [dut0, dut1, dut2, dut3]
vector_string = '''
PI clk
PI rstb
PI in0
PI in1
PI in2
PO out1
PO out2
00 000 00
01 000 00
01 000 00
11 010 10
01 100 00
01 110 10
11 010 10
01 100 00
11 000 00
01 100 00
11 110 10
01 000 00
11 011 00
01 101 10
11 111 01
01 011 01
11 101 11
01 001 11
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire(['clk', 'q0', 'q1', 'q2', 'q3', 'cout', 'cin', 'rstb']))
nn = self.netlist
self.gatelist = [\
count4_nmos( "count4_0_u", dict([('Q0', nn['q0']),('Q1', nn['q1']),('Q2', nn['q2']),('Q3', nn['q3']), \
('COUT',nn['cout']), ('CIN', nn['cin']), ('RSTB', nn['rstb']), \
('PHI',nn['clk'])]), self)
]
vector_string = '''
PI clk
PI rstb
PI cin
PO q3
PO q2
PO q1
PO q0
001 LLLL
011 LLLL
011 LLLL
111 LLLH
011 LLLH
111 LLHL
011 LLHL
111 LLHH
011 LLHH
111 LHLL
011 LHLL
111 LHLH
011 LHLH
111 LHHL
011 LHHL
111 LHHH
011 LHHH
111 HLLL
011 HLLL
111 HLLH
011 HLLH
111 HLHL
011 HLHL
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['clk', 'q0', 'q1', 'rstb']))
nn = self.netlist
self.gatelist = [\
count2_nmos( "count2_0_u", dict([('Q0', nn['q0']),('Q1', nn['q1']),('RSTB', nn['rstb']),('PHI',nn['clk'])]), self)
]
vector_string = '''
PI clk
PI rstb
PO q1
PO q0
00 LL
00 LL
01 LL
01 LL
11 LH
01 LH
11 HL
01 HL
11 HH
01 HH
11 LL
01 LL
11 LH
01 LH
11 HL
01 HL
11 HH
01 HH
11 LL
01 LL
11 LH
01 LH
11 HL
01 HL
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['write']))
self.netlist.update(
gate.wire(['data0_in', 'n10', 'n20', 'bit0', 'bit0_b', 'word0']))
self.netlist.update(
gate.wire(['data1_in', 'n11', 'n21', 'bit1', 'bit1_b', 'word1']))
self.netlist.update(
gate.wire(['data2_in', 'n12', 'n22', 'bit2', 'bit2_b', 'word2']))
self.netlist.update(
gate.wire(['data3_in', 'n13', 'n23', 'bit3', 'bit3_b', 'word3']))
for j in range(0, 4):
for i in range(0, 4):
self.netlist.update(
gate.wire([
'word%d%d' % (i, j),
'q%d%d' % (i, j),
'q%d%d_b' % (i, j)
]))
self.netlist['q%d%d' % (i, j)].pullup_str = net.DEPL_STR
self.netlist['q%d%d_b' % (i, j)].pullup_str = net.DEPL_STR
self.netlist['n1%d' % j].pullup_str = net.DEPL_STR
self.netlist['n2%d' % j].pullup_str = net.DEPL_STR
self.gatelist = []
for j in range(0, 4):
for i in range(0, 4):
self.gatelist.extend([
NMOS("ram%d%d_0_u" % (j, i), [
self.netlist['q%d%d' % (j, i)], self.netlist['vss'],
self.netlist['q%d%d_b' % (j, i)]
],
parent=self),
NMOS("ram%d%d_1_u" % (j, i), [
self.netlist['q%d%d_b' % (j, i)], self.netlist['vss'],
self.netlist['q%d%d' % (j, i)]
],
parent=self),
NMOS("ram%d%d_2_u" % (j, i), [
self.netlist['bit%d' % i], self.netlist['q%d%d' %
(j, i)],
self.netlist['word%d' % j]
],
parent=self),
NMOS("ram%d%d_3_u" % (i, j), [
self.netlist['bit%d_b' % i], self.netlist['q%d%d_b' %
(j, i)],
self.netlist['word%d' % j]
],
parent=self)
])
self.gatelist.extend([
NMOS("ctrl_0%d_u" % j, [
self.netlist['bit%d' % j], self.netlist['n2%d' % j],
self.netlist['write']
], self),
NMOS("ctrl_1%d_u" % j, [
self.netlist['bit%d_b' % j], self.netlist['n1%d' % j],
self.netlist['write']
], self),
NMOS("ctrl_2%d_u" % j, [
self.netlist['n1%d' % j], self.netlist['vss'],
self.netlist['data%d_in' % j]
], self),
NMOS("ctrl_4%d_u" % j, [
self.netlist['n2%d' % j], self.netlist['vss'],
self.netlist['n1%d' % j]
], self)
])
vector_string = '''
PI data3_in
PI data2_in
PI data1_in
PI data0_in
PI write
PI word3
PI word2
PI word1
PI word0
PO q33
PO q32
PO q31
PO q30
PO q23
PO q22
PO q21
PO q20
PO q13
PO q12
PO q11
PO q10
PO q03
PO q02
PO q01
PO q00
PO bit3
PO bit2
PO bit1
PO bit0
PO bit3_b
PO bit2_b
PO bit1_b
PO bit0_b
# dddd
# aaaa
# tttt w wwww bbbb
# aaaa r oooo iiii
# 1010 bbbb tttt
# ____ i rrrr qqqq qqqq qqqq qqqq iiii 3210
# iiii t dddd 3333 2222 1111 0000 tttt ____
# nnnn e 3210 3210 3210 3210 3210 3210 bbbb
# ----------------------------------------------
0000 0 0000 XXXX XXXX XXXX XXXX XXXX XXXX
0000 1 0001 XXXX XXXX XXXX LLLL XXXX XXXX
0000 1 0010 XXXX XXXX LLLL LLLL XXXX XXXX
0000 1 0100 XXXX LLLL LLLL LLLL XXXX XXXX
0000 1 1000 LLLL LLLL LLLL LLLL XXXX XXXX
0000 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0001 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0010 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0100 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 1000 LLLL LLLL LLLL LLLL LLLL HHHH
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 0 0000 LLLL LLLL LLLL LLLL XXXX XXXX
1111 1 0001 LLLL LLLL LLLL HHHH XXXX XXXX
1111 1 0010 LLLL LLLL HHHH HHHH XXXX XXXX
1111 1 0100 LLLL HHHH HHHH HHHH XXXX XXXX
1111 1 1000 HHHH HHHH HHHH HHHH XXXX XXXX
1111 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0001 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0010 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0100 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 1000 HHHH HHHH HHHH HHHH HHHH LLLL
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0000 HHHH HHHH HHHH HHHH XXXX XXXX
0000 0 0001 HHHH HHHH HHHH LLLL XXXX XXXX
0000 0 0000 HHHH HHHH HHHH LLLL XXXX XXXX
0000 0 0100 HHHH LLLL HHHH LLLL XXXX XXXX
0000 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
1111 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
1111 0 0001 HHHH LLLL HHHH LLLL LLLL HHHH
1111 0 0010 HHHH LLLL HHHH LLLL HHHH LLLL
1111 0 0100 HHHH LLLL HHHH LLLL LLLL HHHH
1111 0 1000 HHHH LLLL HHHH LLLL HHHH LLLL
1111 0 0000 HHHH LLLL HHHH LLLL XXXX XXXX
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['data%d_w' % i for i in range(0, 8)]))
self.netlist.update(gate.wire(['addr%02d_w' % i
for i in range(0, 16)]))
self.netlist.update(
gate.wire([
'rstb_w', 'rnw_w', 'sync_w', 'sob_w', 'phi0_w', 'phi1_w',
'phi2_w', 'rdy_w', 'nmib_w', 'irqb_w'
]))
self.netlist['vcc'] = net.supply1('vcc')
self.netlist['vss'] = net.supply0('vss')
self.netlist['vdd'] = net.supply1('vdd')
self.gatelist = [ v6502( "v6502_0_u", dict([\
('res', self.netlist['rstb_w']),
('rw', self.netlist['rnw_w']),
('db0', self.netlist['data0_w']),
('db1', self.netlist['data1_w']),
('db2', self.netlist['data2_w']),
('db3', self.netlist['data3_w']),
('db4', self.netlist['data4_w']),
('db5', self.netlist['data5_w']),
('db6', self.netlist['data6_w']),
('db7', self.netlist['data7_w']),
('ab0', self.netlist['addr00_w']),
('ab1', self.netlist['addr01_w']),
('ab2', self.netlist['addr02_w']),
('ab3', self.netlist['addr03_w']),
('ab4', self.netlist['addr04_w']),
('ab5', self.netlist['addr05_w']),
('ab6', self.netlist['addr06_w']),
('ab7', self.netlist['addr07_w']),
('ab8', self.netlist['addr08_w']),
('ab9', self.netlist['addr09_w']),
('ab10',self.netlist['addr10_w']),
('ab11',self.netlist['addr11_w']),
('ab12',self.netlist['addr12_w']),
('ab13',self.netlist['addr13_w']),
('ab14',self.netlist['addr14_w']),
('ab15',self.netlist['addr15_w']),
('sync',self.netlist['sync_w']),
('so', self.netlist['sob_w']),
('clk0',self.netlist['phi0_w']),
('clk1out',self.netlist['phi1_w']),
('clk2out',self.netlist['phi2_w']),
('rdy', self.netlist['rdy_w']),
('nmi', self.netlist['nmib_w']),
('irq', self.netlist['irqb_w']),
('vss', self.netlist['vss']),
('vcc', self.netlist['vcc']),
])) ]
vector_string = '''
PI rstb_w
PI phi0_w
PI data7_w
PI data6_w
PI data5_w
PI data4_w
PI data3_w
PI data2_w
PI data1_w
PI data0_w
PI sob_w
PI nmib_w
PI irqb_w
PI rdy_w
'''
vectors = []
opcode = '11101000'
reset = '0'
for i in range(0, 4096):
for clockseq in ['0', '1']:
vectors.append(" %s %s %s 10111" % (reset, clockseq, opcode))
if i > 3:
reset = '1'
vector_string += '\n'.join(vectors)
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update( gate.wire(['q%02d' %i for i in range(0,16)]))
self.netlist.update( gate.wire(['qq%02d' %i for i in range(0,16)]))
self.netlist.update( gate.wire(['f%02d' %i for i in range(0,16)]))
self.netlist.update( gate.wire(['s%d' %i for i in range(0,4)]))
self.netlist.update( gate.wire(['aeb%d' %i for i in range(0,4)]))
self.netlist.update( gate.wire(['x%d' %i for i in range(0,4)]))
self.netlist.update( gate.wire(['y%d' %i for i in range(0,4)]))
self.netlist.update( gate.wire(['cn4%d' %i for i in range(0,4)]))
self.netlist.update( gate.wire([ 'rstb', 'phi', 'mode', 'carryin']))
dut0 = count16_bidir_nmos( "cout16_0_u", dict([ ('Q0', self.netlist['q00']),
('Q1', self.netlist['q01']),
('Q2', self.netlist['q02']),
('Q3', self.netlist['q03']),
('Q4', self.netlist['q04']),
('Q5', self.netlist['q05']),
('Q6', self.netlist['q06']),
('Q7', self.netlist['q07']),
('Q8', self.netlist['q08']),
('Q9', self.netlist['q09']),
('Q10', self.netlist['q10']),
('Q11', self.netlist['q11']),
('Q12', self.netlist['q12']),
('Q13', self.netlist['q13']),
('Q14', self.netlist['q14']),
('Q15', self.netlist['q15']),
('CIN', self.netlist['vdd']),
('PHI', self.netlist['phi']),
('RSTB', self.netlist['rstb'])]))
dut1 = count16_bidir_nmos( "cout16_1_u", dict([ ('Q0', self.netlist['qq00']),
('Q1', self.netlist['qq01']),
('Q2', self.netlist['qq02']),
('Q3', self.netlist['qq03']),
('Q4', self.netlist['qq04']),
('Q5', self.netlist['qq05']),
('Q6', self.netlist['qq06']),
('Q7', self.netlist['qq07']),
('Q8', self.netlist['qq08']),
('Q9', self.netlist['qq09']),
('Q10', self.netlist['qq10']),
('Q11', self.netlist['qq11']),
('Q12', self.netlist['qq12']),
('Q13', self.netlist['qq13']),
('Q14', self.netlist['qq14']),
('Q15', self.netlist['qq15']),
('CIN', self.netlist['vdd']),
('PHI', self.netlist['q08']),
('RSTB', self.netlist['rstb'])]))
dut2 = sn74181alu_bidir_nmos( "alu_0_u", dict([ ('A0', self.netlist['q00']),
('A1', self.netlist['q01']),
('A2', self.netlist['q02']),
('A3', self.netlist['q03']),
('B0', self.netlist['qq00']),
('B1', self.netlist['qq01']),
('B2', self.netlist['qq02']),
('B3', self.netlist['qq03']),
('S0', self.netlist['s0']),
('S1', self.netlist['s1']),
('S2', self.netlist['s2']),
('S3', self.netlist['s3']),
('CN', self.netlist['carryin']),
('M', self.netlist['mode']),
('F0', self.netlist['f00']),
('F1', self.netlist['f01']),
('F2', self.netlist['f02']),
('F3', self.netlist['f03']),
('AEB', self.netlist['aeb0']),
('X', self.netlist['x0']),
('Y', self.netlist['y0']),
('CN4', self.netlist['cn40'])]))
dut3 = sn74181alu_bidir_nmos( "alu_1_u", dict([ ('A0', self.netlist['q04']),
('A1', self.netlist['q05']),
('A2', self.netlist['q06']),
('A3', self.netlist['q07']),
('B0', self.netlist['qq04']),
('B1', self.netlist['qq05']),
('B2', self.netlist['qq06']),
('B3', self.netlist['qq07']),
('S0', self.netlist['s0']),
('S1', self.netlist['s1']),
('S2', self.netlist['s2']),
('S3', self.netlist['s3']),
('CN', self.netlist['cn40']),
('M', self.netlist['mode']),
('F0', self.netlist['f04']),
('F1', self.netlist['f05']),
('F2', self.netlist['f06']),
('F3', self.netlist['f07']),
('AEB', self.netlist['aeb1']),
('X', self.netlist['x1']),
('Y', self.netlist['y1']),
('CN4', self.netlist['cn41'])]))
dut4 = sn74181alu_bidir_nmos( "alu_2_u", dict([ ('A0', self.netlist['q08']),
('A1', self.netlist['q09']),
('A2', self.netlist['q10']),
('A3', self.netlist['q11']),
('B0', self.netlist['qq08']),
('B1', self.netlist['qq09']),
('B2', self.netlist['qq10']),
('B3', self.netlist['qq11']),
('S0', self.netlist['s0']),
('S1', self.netlist['s1']),
('S2', self.netlist['s2']),
('S3', self.netlist['s3']),
('CN', self.netlist['cn41']),
('M', self.netlist['mode']),
('F0', self.netlist['f08']),
('F1', self.netlist['f09']),
('F2', self.netlist['f10']),
('F3', self.netlist['f11']),
('AEB', self.netlist['aeb2']),
('X', self.netlist['x2']),
('Y', self.netlist['y2']),
('CN4', self.netlist['cn42'])]))
dut5 = sn74181alu_bidir_nmos( "alu_3_u", dict([ ('A0', self.netlist['q12']),
('A1', self.netlist['q13']),
('A2', self.netlist['q14']),
('A3', self.netlist['q15']),
('B0', self.netlist['qq12']),
('B1', self.netlist['qq13']),
('B2', self.netlist['qq14']),
('B3', self.netlist['qq15']),
('S0', self.netlist['s0']),
('S1', self.netlist['s1']),
('S2', self.netlist['s2']),
('S3', self.netlist['s3']),
('CN', self.netlist['cn43']),
('M', self.netlist['mode']),
('F0', self.netlist['f12']),
('F1', self.netlist['f13']),
('F2', self.netlist['f14']),
('F3', self.netlist['f15']),
('AEB', self.netlist['aeb3']),
('X', self.netlist['x3']),
('Y', self.netlist['y3']),
('CN4', self.netlist['cn43'])]))
self.gatelist = [dut0, dut1, dut2, dut3, dut4, dut5]
vector_string = '''
PI rstb
PI phi
PI s0
PI s1
PI s2
PI s3
PI mode
PI carryin
0 0 1000 00
1 0 1000 00
'''
vector_string += '\n'.join([' 1 0 1000 00\n 1 1 1000 00'] * 65535)
self.events = self.read_flex_string( vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'in0', 'in1', 'in2', 'n0', 'n1', 'n2', 'n2b', 'mx0', 'mx1',
'out', 'out1'
]))
self.netlist['mx0'].charge_storage = True
self.gatelist = [
INV("inv_0_u", [self.netlist['n0'], self.netlist['in0']], self),
INV("inv_1_u", [self.netlist['n1'], self.netlist['in1']], self),
INV("inv_2_u", [self.netlist['n2b'], self.netlist['in2']], self),
BUF("buf_0_u", [self.netlist['n2'], self.netlist['in2']], self),
UNMOS(
"nmos_0_u",
[self.netlist['mx0'], self.netlist['n0'], self.netlist['n2b']],
self),
UNMOS(
"nmos_1_u",
[self.netlist['mx0'], self.netlist['n1'], self.netlist['in2']],
self),
UNMOS(
"nmos_2_u",
[self.netlist['mx1'], self.netlist['n0'], self.netlist['n2b']],
self),
UNMOS(
"nmos_3_u",
[self.netlist['mx1'], self.netlist['n1'], self.netlist['n2']],
self),
INV("inv_3_u", [self.netlist['out'], self.netlist['mx0']], self),
INV("inv_4_u", [self.netlist['out1'], self.netlist['mx1']], self),
]
vector_string = '''
PI in0
PI in1
PI in2
PO out
# o
# iii ou
# nnn ut
# 012 t1
# -------------
000 LL
001 LL
010 LL
011 HH
100 HH
101 LL
110 HH
111 HH
000 LL
001 LL
010 LL
011 HH
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'in0', 'in1', 'in2', 'in3', 'in4', 'in5', 'n0', 'n1', 'n2',
'n3', 'out'
]))
self.netlist['out'].pullup_str = net.DEPL_STR
self.netlist['n0'].pullup_str = net.DEPL_STR
self.netlist['n1'].pullup_str = net.DEPL_STR
self.netlist['n2'].charge_storage = True
self.netlist['n3'].charge_storage = True
self.gatelist = [
NMOS(
"nmos_0_u",
[self.netlist['n0'], self.netlist['vss'], self.netlist['in0']],
self),
NMOS(
"nmos_1_u",
[self.netlist['n1'], self.netlist['vss'], self.netlist['in1']],
self),
NMOS(
"nmos_2_u",
[self.netlist['n2'], self.netlist['vss'], self.netlist['in2']],
self),
NMOS("nmos_3_u",
[self.netlist['n0'], self.netlist['n2'], self.netlist['in3']],
self),
NMOS("nmos_4_u",
[self.netlist['n1'], self.netlist['n2'], self.netlist['in4']],
self),
UNMOS(
"unmos_5_u",
[self.netlist['n3'], self.netlist['n2'], self.netlist['in5']],
self),
NMOS(
"nmos_6_u",
[self.netlist['out'], self.netlist['vss'], self.netlist['n3']],
self),
]
vector_string = '''
PI in0
PI in1
PI in2
PI in3
PI in4
PI in5
PO n2
PO out
# iiiiii o
# nnnnnn n u
# 012345 2 t
# -------------
111111 L H
000000 L H
000100 H H
000001 H L
000000 H L
101010 L L
010101 H L
000110 H L
000101 H L
101000 L L
000001 L H
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(
gate.wire([
'cclk', 'n821', 'n826', 'n318', 'n1062', 'n1315', 'n705',
'out', 'abh0'
]))
self.netlist['n1315'].pullup_str = net.DEPL_STR
self.netlist['abh0'].pullup_str = net.DEPL_STR
self.netlist['n1062'].charge_storage = True
self.gatelist = [
NMOS("nmos_0_u", [
self.netlist['out'], self.netlist['vdd'], self.netlist['n826']
], self),
NMOS("nmos_1_u", [
self.netlist['out'], self.netlist['vss'], self.netlist['n318']
], self),
NMOS("nmos_2_u", [
self.netlist['n318'], self.netlist['vdd'],
self.netlist['n1315']
], self),
NMOS("nmos_3_u", [
self.netlist['n318'], self.netlist['vss'], self.netlist['abh0']
], self),
NMOS("nmos_4_u", [
self.netlist['n826'], self.netlist['vdd'], self.netlist['abh0']
], self),
NMOS("nmos_5_u", [
self.netlist['n826'], self.netlist['vss'], self.netlist['n318']
], self),
NMOS("nmos_6_u", [
self.netlist['n1315'], self.netlist['vss'],
self.netlist['abh0']
], self),
NMOS("nmos_7_u", [
self.netlist['abh0'], self.netlist['vss'],
self.netlist['n1062']
], self),
NMOS("nmos_8_u", [
self.netlist['n318'], self.netlist['n1062'],
self.netlist['cclk']
], self),
NMOS("nmos_9_u", [
self.netlist['n705'], self.netlist['n1062'],
self.netlist['n821']
], self),
]
vector_string = '''
PI n705
PI n821
PI cclk
PO out
001 X
010 H
001 H
101 H
110 L
101 L
001 L
010 H
'''
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['data%d_w' % i for i in range(0, 8)]))
self.netlist.update(gate.wire(['addr%02d_w' % i
for i in range(0, 16)]))
self.netlist.update(
gate.wire([
'rstb_w', 'rnw_w', 'dbe_w', 'tsc_w', 'vma_w', 'ba_w', 'phi1_w',
'phi2_w', 'haltb_w', 'nmib_w', 'irqb_w'
]))
self.netlist['vcc'] = net.supply1('vcc')
self.netlist['vss'] = net.supply0('vss')
self.netlist['vdd'] = net.supply1('vdd')
self.gatelist = [ v6800( "v6800_0_u", dict([\
('reset', self.netlist['rstb_w']),
('rw', self.netlist['rnw_w']),
('db0', self.netlist['data0_w']),
('db1', self.netlist['data1_w']),
('db2', self.netlist['data2_w']),
('db3', self.netlist['data3_w']),
('db4', self.netlist['data4_w']),
('db5', self.netlist['data5_w']),
('db6', self.netlist['data6_w']),
('db7', self.netlist['data7_w']),
('ab0', self.netlist['addr00_w']),
('ab1', self.netlist['addr01_w']),
('ab2', self.netlist['addr02_w']),
('ab3', self.netlist['addr03_w']),
('ab4', self.netlist['addr04_w']),
('ab5', self.netlist['addr05_w']),
('ab6', self.netlist['addr06_w']),
('ab7', self.netlist['addr07_w']),
('ab8', self.netlist['addr08_w']),
('ab9', self.netlist['addr09_w']),
('ab10',self.netlist['addr10_w']),
('ab11',self.netlist['addr11_w']),
('ab12',self.netlist['addr12_w']),
('ab13',self.netlist['addr13_w']),
('ab14',self.netlist['addr14_w']),
('ab15',self.netlist['addr15_w']),
('vma',self.netlist['vma_w']),
('ba', self.netlist['ba_w']),
('dbe', self.netlist['phi2_w']),
('tsc', self.netlist['tsc_w']),
('phi1',self.netlist['phi1_w']),
('phi2',self.netlist['phi2_w']),
('halt', self.netlist['haltb_w']),
('nmi', self.netlist['nmib_w']),
('irq', self.netlist['irqb_w']),
('gnd', self.netlist['vss']),
('vcc', self.netlist['vcc']),
])) ]
vector_string = '''
PI rstb_w
PI phi1_w
PI phi2_w
PI data7_w
PI data6_w
PI data5_w
PI data4_w
PI data3_w
PI data2_w
PI data1_w
PI data0_w
PI dbe_w
PI tsc_w
PI nmib_w
PI irqb_w
PI haltb_w
'''
vectors = []
opcode = '00000001'
reset = '0'
for i in range(0, 2048):
for clockseq in ['00', '01', '00', '10']:
vectors.append(" %s %s %s 10111" % (reset, clockseq, opcode))
if i > 3:
reset = '1'
vector_string += '\n'.join(vectors)
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['data%d_w' % i for i in range(0, 8)]))
self.netlist.update(gate.wire(['addr%02d_w' % i
for i in range(0, 16)]))
self.netlist.update(
gate.wire([
'clk_w', '_reset_w', '_wait_w', '_int_w', '_nmi_w', '_busrq_w',
'_m1_w', '_rd_w', '_wr_w', '_mreq_w', '_iorq_w', '_rfsh_w',
'_halt_w', '_busak_w'
]))
self.netlist['vcc'] = net.supply1('vcc')
self.netlist['vss'] = net.supply0('vss')
self.netlist['vdd'] = net.supply1('vdd')
self.gatelist = [ v80( "v80_0_u", dict([\
('clk', self.netlist['clk_w']),
('ab0', self.netlist['addr00_w']),
('ab1', self.netlist['addr01_w']),
('ab2', self.netlist['addr02_w']),
('ab3', self.netlist['addr03_w']),
('ab4', self.netlist['addr04_w']),
('ab5', self.netlist['addr05_w']),
('ab6', self.netlist['addr06_w']),
('ab7', self.netlist['addr07_w']),
('ab8', self.netlist['addr08_w']),
('ab9', self.netlist['addr09_w']),
('ab10', self.netlist['addr10_w']),
('ab11', self.netlist['addr11_w']),
('ab12', self.netlist['addr12_w']),
('ab13', self.netlist['addr13_w']),
('ab14', self.netlist['addr14_w']),
('ab15', self.netlist['addr15_w']),
('_reset', self.netlist['_reset_w']),
('_wait', self.netlist['_wait_w']),
('_int', self.netlist['_int_w']),
('_nmi', self.netlist['_nmi_w']),
('_busrq', self.netlist['_busrq_w']),
('_m1', self.netlist['_m1_w']),
('_rd', self.netlist['_rd_w']),
('_wr', self.netlist['_wr_w']),
('_mreq', self.netlist['_mreq_w']),
('_iorq', self.netlist['_iorq_w']),
('_rfsh', self.netlist['_rfsh_w']),
('db0', self.netlist['data0_w']),
('db1', self.netlist['data1_w']),
('db2', self.netlist['data2_w']),
('db3', self.netlist['data3_w']),
('db4', self.netlist['data4_w']),
('db5', self.netlist['data5_w']),
('db6', self.netlist['data6_w']),
('db7', self.netlist['data7_w']),
('_halt', self.netlist['_halt_w']),
('_busak', self.netlist['_busak_w']),
('vss', self.netlist['vss']),
('vcc', self.netlist['vcc']),
])) ]
vector_string = '''
PI _reset_w
PI clk_w
PI data7_w
PI data6_w
PI data5_w
PI data4_w
PI data3_w
PI data2_w
PI data1_w
PI data0_w
PI _wait_w
PI _int_w
PI _nmi_w
PI _busrq_w
'''
vectors = []
opcode = '00000000'
reset = '0'
for i in range(0, 4096):
for clockseq in ['0', '1']:
vectors.append(" %s %s %s 1111" % (reset, clockseq, opcode))
if i > 10:
reset = '1'
vector_string += '\n'.join(vectors)
self.events = self.read_flex_string(vector_string)
(port[2], expect_table[c], 'pi'))
elif c == '1' or c == '0' or c == 'Z':
if prev_drive_data[port[0]] != c:
pi_events.append(
(port[2], (c, 0), self.pins[port[0]]))
prev_drive_data[port[0]] = c
events.append((pi_events, po_events))
return events
if __name__ == '__main__':
v = '''
# comment
PI A
PI B
PO C
IO_HL D
11HL
11LH # comment
11LL
10HZ
'''
tb = testbench.testbench('dummy')
tb.netlist = dict()
tb.netlist.update(gate.wire(['A', 'B', 'C', 'D']))
tb.read_flex_string(v)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['data%d_w' % i for i in range(0, 8)]))
self.netlist.update(gate.wire(['addr%02d_w' % i
for i in range(0, 16)]))
self.netlist.update(
gate.wire([
'rstb_w', 'rnw_w', 'tsc_w', 'haltb_w', 'vma_w', 'phi1_w',
'phi2_w', 'phi2b_w', 'ba_w', 'nmib_w', 'irqb_w', 'not_addr15_w'
]))
self.netlist.update(gate.wire(["web_w"]))
self.netlist['vcc'] = net.supply1('vcc')
self.netlist['vss'] = net.supply0('vss')
self.netlist['vdd'] = net.supply1('vdd')
self.gatelist = [ v6800( "v6800_0_u", dict([\
('reset', self.netlist['rstb_w']),
('rw', self.netlist['rnw_w']),
('db0', self.netlist['data0_w']),
('db1', self.netlist['data1_w']),
('db2', self.netlist['data2_w']),
('db3', self.netlist['data3_w']),
('db4', self.netlist['data4_w']),
('db5', self.netlist['data5_w']),
('db6', self.netlist['data6_w']),
('db7', self.netlist['data7_w']),
('ab0', self.netlist['addr00_w']),
('ab1', self.netlist['addr01_w']),
('ab2', self.netlist['addr02_w']),
('ab3', self.netlist['addr03_w']),
('ab4', self.netlist['addr04_w']),
('ab5', self.netlist['addr05_w']),
('ab6', self.netlist['addr06_w']),
('ab7', self.netlist['addr07_w']),
('ab8', self.netlist['addr08_w']),
('ab9', self.netlist['addr09_w']),
('ab10',self.netlist['addr10_w']),
('ab11',self.netlist['addr11_w']),
('ab12',self.netlist['addr12_w']),
('ab13',self.netlist['addr13_w']),
('ab14',self.netlist['addr14_w']),
('ab15',self.netlist['addr15_w']),
('phi1',self.netlist['phi1_w']),
('phi2',self.netlist['phi2_w']),
('irq', self.netlist['irqb_w']),
('nmi', self.netlist['nmib_w']),
('halt', self.netlist['haltb_w']),
('tsc',self.netlist['tsc_w']),
('ba', self.netlist['ba_w']),
('vma', self.netlist['vma_w']),
('dbe', self.netlist['phi2_w']),
('gnd', self.netlist['vss']),
('vcc', self.netlist['vcc']),
])) ]
self.gatelist.append( rom32k( "rom32k_0_u", dict([\
('oeb', self.netlist['phi2b_w']),
('csb', self.netlist['not_addr15_w']),
('adr00', self.netlist['addr00_w']),
('adr01', self.netlist['addr01_w']),
('adr02', self.netlist['addr02_w']),
('adr03', self.netlist['addr03_w']),
('adr04', self.netlist['addr04_w']),
('adr05', self.netlist['addr05_w']),
('adr06', self.netlist['addr06_w']),
('adr07', self.netlist['addr07_w']),
('adr08', self.netlist['addr08_w']),
('adr09', self.netlist['addr09_w']),
('adr10', self.netlist['addr10_w']),
('adr11', self.netlist['addr11_w']),
('adr12', self.netlist['addr12_w']),
('adr13', self.netlist['addr13_w']),
('adr14', self.netlist['addr14_w']),
('data0', self.netlist['data0_w']),
('data1', self.netlist['data1_w']),
('data2', self.netlist['data2_w']),
('data3', self.netlist['data3_w']),
('data4', self.netlist['data4_w']),
('data5', self.netlist['data5_w']),
('data6', self.netlist['data6_w']),
('data7', self.netlist['data7_w']),]), \
adr_lo=0x8000,\
filename=self.options["rom_filename"]\
))
self.gatelist.append( ram32k( "ram32k_0_u", dict([\
('oeb', self.netlist['phi2b_w']),
('csb', self.netlist['addr15_w']),
('web', self.netlist['web_w']),
('adr00', self.netlist['addr00_w']),
('adr01', self.netlist['addr01_w']),
('adr02', self.netlist['addr02_w']),
('adr03', self.netlist['addr03_w']),
('adr04', self.netlist['addr04_w']),
('adr05', self.netlist['addr05_w']),
('adr06', self.netlist['addr06_w']),
('adr07', self.netlist['addr07_w']),
('adr08', self.netlist['addr08_w']),
('adr09', self.netlist['addr09_w']),
('adr10', self.netlist['addr10_w']),
('adr11', self.netlist['addr11_w']),
('adr12', self.netlist['addr12_w']),
('adr13', self.netlist['addr13_w']),
('adr14', self.netlist['addr14_w']),
('data0', self.netlist['data0_w']),
('data1', self.netlist['data1_w']),
('data2', self.netlist['data2_w']),
('data3', self.netlist['data3_w']),
('data4', self.netlist['data4_w']),
('data5', self.netlist['data5_w']),
('data6', self.netlist['data6_w']),
('data7', self.netlist['data7_w'])]),\
adr_lo=0x0000,))
self.gatelist.append(
INV("inv_0_u",
[self.netlist['not_addr15_w'], self.netlist['addr15_w']]))
# NB - for 6800 phi2b != phi1 ! Clocks have to be non-overlapping
self.gatelist.append(
INV("inv_1_u", [self.netlist['phi2b_w'], self.netlist['phi2_w']]))
self.gatelist.append(
OR("or_0_u", [
self.netlist['web_w'], self.netlist['rnw_w'],
self.netlist['phi2b_w']
]))
vector_string = '''
PI rstb_w
PI phi1_w
PI phi2_w
PI tsc_w
PI nmib_w
PI irqb_w
PI haltb_w
'''
vectors = []
reset = '0'
for i in range(0, 8192):
for clockseq in ['00', '10', '00', '01']:
vectors.append(" %s %s 0111" % (reset, clockseq))
if i > 3:
reset = '1'
vector_string += '\n'.join(vectors)
self.events = self.read_flex_string(vector_string)
def __init__(self, options):
testbench.__init__(self, options)
self.netlist.update(gate.wire(['data%d_w' % i for i in range(0, 8)]))
self.netlist.update(gate.wire(['addr%02d_w' % i
for i in range(0, 16)]))
self.netlist.update(
gate.wire([
'rstb_w', 'rnw_w', 'sync_w', 'sob_w', 'phi0_w', 'phi1_w',
'phi2_w', 'rdy_w', 'nmib_w', 'irqb_w', 'not_addr15_w'
]))
self.netlist.update(
gate.wire([
'rstb_w', 'rnw_w', 'sync_w', 'sob_w', 'phi0_w', 'phi1_w',
'phi2_w', 'rdy_w', 'nmib_w', 'irqb_w'
]))
self.netlist.update(gate.wire(['not_addr15_w', "web_w"]))
self.netlist['vcc'] = net.supply1('vcc')
self.netlist['vss'] = net.supply0('vss')
self.netlist['vdd'] = net.supply1('vdd')
self.gatelist = [ v6502( "v6502_0_u", dict([\
('res', self.netlist['rstb_w']),
('rw', self.netlist['rnw_w']),
('db0', self.netlist['data0_w']),
('db1', self.netlist['data1_w']),
('db2', self.netlist['data2_w']),
('db3', self.netlist['data3_w']),
('db4', self.netlist['data4_w']),
('db5', self.netlist['data5_w']),
('db6', self.netlist['data6_w']),
('db7', self.netlist['data7_w']),
('ab0', self.netlist['addr00_w']),
('ab1', self.netlist['addr01_w']),
('ab2', self.netlist['addr02_w']),
('ab3', self.netlist['addr03_w']),
('ab4', self.netlist['addr04_w']),
('ab5', self.netlist['addr05_w']),
('ab6', self.netlist['addr06_w']),
('ab7', self.netlist['addr07_w']),
('ab8', self.netlist['addr08_w']),
('ab9', self.netlist['addr09_w']),
('ab10',self.netlist['addr10_w']),
('ab11',self.netlist['addr11_w']),
('ab12',self.netlist['addr12_w']),
('ab13',self.netlist['addr13_w']),
('ab14',self.netlist['addr14_w']),
('ab15',self.netlist['addr15_w']),
('sync',self.netlist['sync_w']),
('so', self.netlist['sob_w']),
('clk0',self.netlist['phi0_w']),
('clk1out',self.netlist['phi1_w']),
('clk2out',self.netlist['phi2_w']),
('rdy', self.netlist['rdy_w']),
('nmi', self.netlist['nmib_w']),
('irq', self.netlist['irqb_w']),
('vss', self.netlist['vss']),
('vcc', self.netlist['vcc']),
])) ]
self.gatelist.append( rom32k( "rom32k_0_u", dict([\
('oeb', self.netlist['phi1_w']),
('csb', self.netlist['not_addr15_w']),
('adr00', self.netlist['addr00_w']),
('adr01', self.netlist['addr01_w']),
('adr02', self.netlist['addr02_w']),
('adr03', self.netlist['addr03_w']),
('adr04', self.netlist['addr04_w']),
('adr05', self.netlist['addr05_w']),
('adr06', self.netlist['addr06_w']),
('adr07', self.netlist['addr07_w']),
('adr08', self.netlist['addr08_w']),
('adr09', self.netlist['addr09_w']),
('adr10', self.netlist['addr10_w']),
('adr11', self.netlist['addr11_w']),
('adr12', self.netlist['addr12_w']),
('adr13', self.netlist['addr13_w']),
('adr14', self.netlist['addr14_w']),
('data0', self.netlist['data0_w']),
('data1', self.netlist['data1_w']),
('data2', self.netlist['data2_w']),
('data3', self.netlist['data3_w']),
('data4', self.netlist['data4_w']),
('data5', self.netlist['data5_w']),
('data6', self.netlist['data6_w']),
('data7', self.netlist['data7_w']),]), \
adr_lo=0x8000,\
filename=self.options["rom_filename"]\
))
self.gatelist.append( ram32k( "ram32k_0_u", dict([\
('oeb', self.netlist['phi1_w']),
('csb', self.netlist['addr15_w']),
('web', self.netlist['web_w']),
('adr00', self.netlist['addr00_w']),
('adr01', self.netlist['addr01_w']),
('adr02', self.netlist['addr02_w']),
('adr03', self.netlist['addr03_w']),
('adr04', self.netlist['addr04_w']),
('adr05', self.netlist['addr05_w']),
('adr06', self.netlist['addr06_w']),
('adr07', self.netlist['addr07_w']),
('adr08', self.netlist['addr08_w']),
('adr09', self.netlist['addr09_w']),
('adr10', self.netlist['addr10_w']),
('adr11', self.netlist['addr11_w']),
('adr12', self.netlist['addr12_w']),
('adr13', self.netlist['addr13_w']),
('adr14', self.netlist['addr14_w']),
('data0', self.netlist['data0_w']),
('data1', self.netlist['data1_w']),
('data2', self.netlist['data2_w']),
('data3', self.netlist['data3_w']),
('data4', self.netlist['data4_w']),
('data5', self.netlist['data5_w']),
('data6', self.netlist['data6_w']),
('data7', self.netlist['data7_w'])]),\
adr_lo=0x0000,))
self.gatelist.append(
INV("inv_0_u",
[self.netlist['not_addr15_w'], self.netlist['addr15_w']]))
self.gatelist.append(
OR("or_0_u", [
self.netlist['web_w'], self.netlist['rnw_w'],
self.netlist['phi1_w']
]))
vector_string = '''
PI rstb_w
PI phi0_w
PI sob_w
PI nmib_w
PI irqb_w
PI rdy_w
'''
vectors = []
reset = '0'
for i in xrange(0, 1024 * 1024):
for clockseq in ['0', '1']:
vectors.append(" %s %s 10111" % (reset, clockseq))
if i > 3:
reset = '1'
vector_string += '\n'.join(vectors)
self.events = self.read_flex_string(vector_string)
