def test_ip_available(): with tempfile.NamedTemporaryFile() as f: path = pathlib.Path(f.name) parent = path.parent assert parent.is_dir() assert ip_available(path.name, [str(parent)]) assert not ip_available("random_file", ["/some/bad/path/"])
"cfg_ifc.svp", "global_controller/genesis/" "global_controller.svp", "global_controller/genesis/jtag.svp", "global_controller/genesis/axi_ctrl.svp", "global_controller/genesis/tap.svp", "global_controller/genesis/cfg_and_dbg.svp", "global_controller/genesis/flop.svp"], params) files = glob.glob('genesis_verif/*') # append path to TAP IP on kiwi files += ["/cad/synopsys/syn/M-2017.06-SP3/dw/sim_ver/DW_tap.v"] return run_verilog_sim(files, cleanup=True) @pytest.mark.skipif(not verilog_sim_available(), reason="verilog simulator not available") @pytest.mark.skipif(not ip_available("DW_tap.v", ["/cad/synopsys/syn/" "M-2017.06-SP3/dw/sim_ver/"]), reason="TAP IP not available") @pytest.mark.parametrize('params', [ { "cfg_bus_width": 32, "cfg_addr_width": 32, "cfg_op_width": 5, } ]) def test_global_controller_verilog_sim(params): res = run_verilog_regression(params) assert res == 1
"global_controller/genesis/axi_ctrl.svp", "global_controller/genesis/tap.svp", "global_controller/genesis/cfg_and_dbg.svp", "global_controller/genesis/flop.svp" ], params) files = glob.glob('genesis_verif/*') # append path to TAP IP on kiwi files += [ "/cad/cadence/GENUS17.21.000.lnx86/share/synth/lib/" "chipware/sim/verilog/CW/CW_tap.v" ] return run_verilog_sim(files, cleanup=True) @pytest.mark.skipif(not verilog_sim_available(), reason="verilog simulator not available") @pytest.mark.skipif(not ip_available("CW_tap.v", [ "/cad/cadence/GENUS17.21.000.lnx86/" "share/synth/lib/chipware/sim/" "verilog/CW/" ]), reason="TAP IP not available") @pytest.mark.parametrize('params', [{ "cfg_bus_width": 32, "cfg_addr_width": 32, "cfg_op_width": 5, }]) def test_global_controller_verilog_sim(params): res = run_verilog_regression(params) assert res == 1
import os from gemstone.common.util import ip_available from gemstone.common.run_verilog_sim import verilog_sim_available import pytest @pytest.mark.skipif(not verilog_sim_available(), reason="verilog simulator not available") @pytest.mark.skipif(not ip_available("CW_tap.v", [ "/cad/cadence/GENUS_19.10.000_lnx86/" "share/synth/lib/chipware/sim/verilog/CW" ]), reason="TAP IP not available") def test_global_controller_verilog_sim(): result = os.system("make -C global_controller sim") assert result == 0
import os from gemstone.common.util import ip_available from gemstone.common.run_verilog_sim import verilog_sim_available import pytest @pytest.mark.skipif(not verilog_sim_available(), reason="verilog simulator not available") @pytest.mark.skipif(not ip_available("DW_tap.v", ["/cad/synopsys/syn/" "P-2019.03/dw/sim_ver"]), reason="TAP IP not available") def test_global_controller_verilog_sim(): result = os.system("make -C global_controller tb_compile") assert result == 0