def add_pipeline(self):
sram_signals_reset_high_in = concat(self.WEB, self.CEB, self.web_demux,
self.ceb_demux, self.BWEB)
sram_signals_reset_high_out = concat(self.WEB_d, self.CEB_d,
self.web_demux_d,
self.ceb_demux_d, self.BWEB_d)
self.sram_signals_reset_high_pipeline = Pipeline(
width=sram_signals_reset_high_in.width,
depth=self._params.sram_gen_pipeline_depth,
reset_high=True)
self.add_child("sram_signals_reset_high_pipeline",
self.sram_signals_reset_high_pipeline,
clk=self.CLK,
clk_en=const(1, 1),
reset=self.RESET,
in_=sram_signals_reset_high_in,
out_=sram_signals_reset_high_out)
sram_signals_in = concat(self.a_sram, self.sram_sel, self.D)
sram_signals_out = concat(self.a_sram_d, self.sram_sel_d, self.D_d)
self.sram_signals_pipeline = Pipeline(
width=sram_signals_in.width,
depth=self._params.sram_gen_pipeline_depth)
self.add_child("sram_signals_pipeline",
self.sram_signals_pipeline,
clk=self.CLK,
clk_en=const(1, 1),
reset=self.RESET,
in_=sram_signals_in,
out_=sram_signals_out)
self.sram_signals_output_pipeline = Pipeline(
width=self.sram_macro_width,
depth=self._params.sram_gen_output_pipeline_depth)
self.add_child("sram_signals_output_pipeline",
self.sram_signals_output_pipeline,
clk=self.CLK,
clk_en=const(1, 1),
reset=self.RESET,
in_=self.Q_w,
out_=self.Q)
def add_sram_cfg_rd_addr_sel_pipeline(self):
self.sram_cfg_rd_addr_sel_d = self.var("sram_cfg_rd_addr_sel_d", 1)
self.sram_cfg_rd_addr_sel_pipeline = Pipeline(
width=1, depth=self.bank_ctrl_pipeline_depth)
self.add_child(
"sram_cfg_rd_addr_sel_pipeline",
self.sram_cfg_rd_addr_sel_pipeline,
clk=self.clk,
clk_en=const(1, 1),
reset=self.reset,
in_=self.if_sram_cfg_s.rd_addr[self._params.bank_byte_offset - 1],
out_=self.sram_cfg_rd_addr_sel_d)
def add_pipeline(self):
self.mem_pipeline = Pipeline(
width=self.data_width,
depth=(self._params.sram_gen_pipeline_depth +
self._params.sram_gen_output_pipeline_depth))
self.add_child("mem_pipeline",
self.mem_pipeline,
clk=self.CLK,
clk_en=const(1, 1),
reset=self.RESET,
in_=self.Q_w,
out_=self.Q)
def add_rd_en_pipeline(self):
self.mem_rd_en_w = self.var("mem_rd_en_w", 1)
self.mem_rd_en_d = self.var("mem_rd_en_d", 1)
self.sram_cfg_rd_en_d = self.var("sram_cfg_rd_en_d", 1)
self.packet_rd_en_d = self.var("packet_rd_en_d", 1)
self.wire(self.mem_rd_en_w, self.mem_rd_en)
self.mem_rd_en_pipeline = Pipeline(width=1,
depth=self.bank_ctrl_pipeline_depth)
self.add_child("mem_rd_en_pipeline",
self.mem_rd_en_pipeline,
clk=self.clk,
clk_en=const(1, 1),
reset=self.reset,
in_=self.mem_rd_en_w,
out_=self.mem_rd_en_d)
self.sram_cfg_rd_en_pipeline = Pipeline(
width=1, depth=self.bank_ctrl_pipeline_depth)
self.add_child("sram_cfg_rd_en_pipeline",
self.sram_cfg_rd_en_pipeline,
clk=self.clk,
clk_en=const(1, 1),
reset=self.reset,
in_=self.if_sram_cfg_s.rd_en,
out_=self.sram_cfg_rd_en_d)
self.packet_rd_en_pipeline = Pipeline(
width=1, depth=self.bank_ctrl_pipeline_depth)
self.add_child("packet_rd_en_pipeline",
self.packet_rd_en_pipeline,
clk=self.clk,
clk_en=const(1, 1),
reset=self.reset,
in_=self.packet_rd_en,
out_=self.packet_rd_en_d)
def add_done_pulse_pipeline(self):
maximum_latency = 2 * self._params.num_glb_tiles + self.default_latency
latency_width = clog2(maximum_latency)
self.done_pulse_d_arr = self.var(
"done_pulse_d_arr", 1, size=maximum_latency, explicit_array=True)
self.done_pulse_pipeline = Pipeline(width=1,
depth=maximum_latency,
flatten_output=True)
self.add_child("done_pulse_pipeline",
self.done_pulse_pipeline,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
in_=self.done_pulse_w,
out_=self.done_pulse_d_arr)
self.wire(self.st_dma_done_pulse,
self.done_pulse_d_arr[resize(self.cfg_data_network_latency, latency_width) + self.default_latency])
def add_strm_rd_addr_pipeline(self):
maximum_latency = 2 * self._params.num_glb_tiles + self.default_latency
latency_width = clog2(maximum_latency)
self.strm_rd_addr_d_arr = self.var("strm_rd_addr_d_arr",
width=self._params.glb_addr_width,
size=maximum_latency,
explicit_array=True)
self.strm_rd_addr_pipeline = Pipeline(
width=self._params.glb_addr_width,
depth=maximum_latency,
flatten_output=True)
self.add_child("strm_rd_addr_pipeline",
self.strm_rd_addr_pipeline,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
in_=self.strm_rd_addr_w,
out_=self.strm_rd_addr_d_arr)
self.strm_data_sel = self.strm_rd_addr_d_arr[
resize(self.cfg_data_network_latency, latency_width) +
self.default_latency][self._params.bank_byte_offset - 1,
self._params.cgra_byte_offset]