def create_addac4_tvs():
a, sel0, sel1, clk = (Wire() for _ in range(4))
s, cout = Wire(), Wire()
Addac4(a=a, sel0=sel0, sel1=sel1, clk=clk, s=s, cout=cout)
file = open('../simulation/modelsim/addac4.tv', 'w')
file.write('0_0_0000_0_x_xxxx\n')
file.write('0_0_0000_1_x_xxxx\n')
file.write('0_0_0000_0_x_xxxx\n')
for s0, s1 in [(0, 0), (1, 0)]:
sel0.set(s0)
sel1.set(s1)
for i in range(120): # 60 casos de teste para cada função
if randint(0, 2) == 0: # inverte clock 1/3 de chance
clock = 1 - clk.data
clk.set(clock)
else: # inverte entrada 2/3 de chance
data = randint(0, 15)
a.set(data)
# sel0_sel1_a_clk_cout_s
file.write('{:1b}_{:1b}_{:04b}_{:1b}_{:1b}_{:04b}\n'.format(
sel0, sel1, a, clk, cout, s))
file.close()
def create_inv_tvs():
a = Wire()
y = Wire()
Inv(a, y)
file = open('../simulation/modelsim/inv.tv', 'w')
for i in [0, 1]:
a.set(i)
# a_y
file.write("{:1b}_{:1b}\n".format(a, y))
file.close()
def create_addac_tvs():
a, sel0, sel1, clk = Wire(), Wire(), Wire(), Wire()
s, cout = Wire(), Wire()
Addac(a=a, sel0=sel0, sel1=sel1, clk=clk, s=s, cout=cout, cin=sel0)
file = open('../simulation/modelsim/addac.tv', 'w')
# borda de subida no começo para inicializar o acumulador
file.write('0_0_0_0_x_x\n')
file.write('0_0_0_1_x_x\n')
file.write('0_0_0_0_x_x\n')
for s0 in [0, 1]:
sel0.set(s0)
for s1 in [0, 1]:
sel1.set(s1)
for i in range(15): # 15 casos de teste para cada função
if randint(0, 2) == 0: # inverte clock 1/3 de chance
clock = 1 - clk.data
clk.set(clock)
else: # inverte entrada 2/3 de chance
data = 1 - a.data
a.set(data)
# sel0_sel1_a_clk_cout_s
file.write('{:1b}_{:1b}_{:1b}_{:1b}_{:1b}_{:1b}\n'.format(
sel0, sel1, a, clk, cout, s))
file.close()
return
def __init__(self, a: Wire, sel0: Wire, sel1: Wire, clk: Wire, cin: Wire,
s: Wire, cout: Wire):
a_inv = Wire()
Inv(a=a, y=a_inv)
mux0_y = Wire()
Mux(d0=a, d1=a_inv, sel=sel0, y=mux0_y)
acc_y, adder_y = Wire(), Wire()
Adder(a=mux0_y, b=acc_y, cin=cin, s=adder_y, cout=cout)
Mux(d0=mux0_y, d1=adder_y, sel=sel1, y=s)
Acc(a=s, clk=clk, y=acc_y)
def __init__(self, a: Wire, sel0: Wire, sel1: Wire, clk: Wire, s: Wire,
cout: Wire):
a_bits = [Wire() for _ in range(4)]
WireSplitter(a, a_bits)
s_bits = [Wire() for _ in range(4)]
WireJoiner(s_bits, s)
addacs_cout = [Wire() for _ in range(3)]
Addac(a=a_bits[0],
sel0=sel0,
sel1=sel1,
clk=clk,
cin=sel0,
s=s_bits[0],
cout=addacs_cout[0])
Addac(a=a_bits[1],
sel0=sel0,
sel1=sel1,
clk=clk,
cin=addacs_cout[0],
s=s_bits[1],
cout=addacs_cout[1])
Addac(a=a_bits[2],
sel0=sel0,
sel1=sel1,
clk=clk,
cin=addacs_cout[1],
s=s_bits[2],
cout=addacs_cout[2])
Addac(a=a_bits[3],
sel0=sel0,
sel1=sel1,
clk=clk,
cin=addacs_cout[2],
s=s_bits[3],
cout=cout)
def add_input(self, name: str, a: Wire):
if name in self.inputs:
self.inputs[name].remove_listener(self)
self.inputs[name] = a
a.listen(self)
def create_mux_tvs():
d0 = Wire()
d1 = Wire()
sel = Wire()
y = Wire()
Mux(d0=d0, d1=d1, sel=sel, y=y)
file = open('../simulation/modelsim/mux.tv', 'w')
for i0 in [0, 1]:
d0.set(i0)
for i1 in [0, 1]:
d1.set(i1)
for s in [0, 1]:
sel.set(s)
# d0_d1_sel_y
file.write("{:1b}_{:1b}_{:1b}_{:1b}\n".format(d0, d1, sel, y))
file.close()