def test():
orig = convert_by_veriloggen_led.mkLed()
conv = hardcheck.convert(orig)
code = conv.to_verilog()
from pyverilog.vparser.parser import VerilogParser
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
parser = VerilogParser()
expected_ast = parser.parse(expected_verilog)
codegen = ASTCodeGenerator()
expected_code = codegen.visit(expected_ast)
assert (expected_code == code)
from veriloggen import *
import hardcheck
def mkLed():
m = Module('blinkled')
width = m.Parameter('WIDTH', 8)
clk = m.Input('CLK')
rst = m.Input('RST')
led = m.OutputReg('LED', width)
count = m.Reg('count', 32)
m.Always(Posedge(clk))(If(rst)(count(0)).Else(
If(count == 1023)(count(0)).Else(count(count + 1))))
m.Always(Posedge(clk))(If(rst)(led(0)).Else(
If(count == 1024 - 1)(led(led + 1))))
return m
if __name__ == '__main__':
orig = mkLed()
#orig_verilog = orig.to_verilog()
#print(orig_verilog)
conv = hardcheck.convert(orig)
conv_verilog = conv.to_verilog()
print(conv_verilog)