def getBaseNameScope(cls):
"""
Get root of name space
"""
s = NameScope.make_top(False)
s.update(cls._keywords_dict)
return s
def netlistToVhdlStr(name: str, netlist: RtlNetlist,
interfaces: Dict[RtlSignal, DIRECTION]):
name_scope = NameScope(None, name, True)
buff = StringIO()
store_manager = SaveToStream(Vhdl2008Serializer, buff)
netlist.create_HdlModuleDec(name, store_manager, {})
netlist.interfaces = interfaces
for s, d in interfaces.items():
s._interface = True
pi = portItemfromSignal(s, netlist, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
netlist.ent.ports.append(pi)
netlist.ent.ports.sort(key=lambda x: x.name)
netlist.create_HdlModuleDef(DummyPlatform(), store_manager)
store_manager.write(netlist.arch)
return buff.getvalue()
def __repr__(self):
from hwt.serializer.hwt import HwtSerializer
name_scope = NameScope(None, "debug", False, debug=True)
to_hdl = HwtSerializer.TO_HDL_AST(name_scope)
to_hdl.debug = True
hdl = to_hdl.as_hdl(self)
buff = StringIO()
# import sys
# buff = sys.stdout
ser = HwtSerializer.TO_HDL(buff)
ser.visit_iHdlObj(hdl)
return buff.getvalue()
def createTwoAxiDuplexStreams():
i = AxiStreamFullDuplex()
i._name = 'i'
i._loadDeclarations()
i._setDirectionsLikeIn(INTF_DIRECTION.MASTER)
i2 = AxiStreamFullDuplex()
i2._name = 'i2'
i2._loadDeclarations()
i2._setDirectionsLikeIn(INTF_DIRECTION.SLAVE)
ns = NameScope(None, "", False)
n = RtlNetlist()
for _i in [i, i2]:
_i._signalsForInterface(n, None, ns)
return i, i2
def verilog_to_hwt(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
#wrap_module_statements_to_processes(context)
InjectProcessSensToStatements().visit_HdlContext(context)
BasicHdlSimModelTranslateVerilogOperands().visit_HdlContext(context)
VerilogTypesToHwt().visit_HdlContext(context)
return context, name_scope
def verilog_to_basic_hdl_sim_model(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
wrap_module_statements_to_processes(context)
BasicHdlSimModelTranslateVerilogOperands().visit_HdlContext(context)
VerilogTypesToBasicHdlSimModel().visit_HdlContext(context)
stm_outputs = discover_stm_outputs_context(context)
AddUniqueLabelsToAllProcesses(name_scope, stm_outputs).context(context)
AssignmentToUpdateAssignment().visit_HdlContext(context)
ApplyIoScopeToSignalNames().visit_HdlContext(context)
return context, stm_outputs, name_scope
def verilog_to_hwt(context):
"""
:type context: HdlContext
"""
link_module_dec_def(context)
name_scope = NameScope.make_top(False)
propopulate_verilog_builtins(name_scope)
DiscoverDeclarations(name_scope).visit_HdlContext(context)
ResolveNames(name_scope).visit_HdlContext(context)
DetectCompileTimeStatements().visit_HdlContext(context)
InjectProcessSensToStatements().visit_HdlContext(context)
BasicHdlSimModelTranslateVerilogOperands(
downto_to_slice_fn=False).visit_HdlContext(context)
VerilogTypesToHwt().visit_HdlContext(context)
AddCallOperatorForCallWithoutParenthesis().visit_HdlContext(context)
wrap_module_statements_to_processes(context)
SignalAssignmentsToCallOp().visit_HdlContext(context)
return context, name_scope
def check_file(self, name, to_hdl_cls):
"""
Load AST from json and convert it to target language
and compare it with reference file
"""
json_suffix, ref_file_suffix = self.FILE_SUFFIX[to_hdl_cls]
d = parse_hdlConvertor_json_file(os.path.join(ROOT,
name + json_suffix))
buff = StringIO()
ser = to_hdl_cls(buff)
if to_hdl_cls is ToBasicHdlSimModel:
# it is required to know outputs of each process
stm_outputs = discover_stm_outputs_context(d)
stm_outputs = rm_ToBasicHdlSimModel_io_prefix_and_tmp_vars_from_outputs(
stm_outputs)
ser.visit_HdlContext(d, stm_outputs)
else:
if to_hdl_cls is ToHwt:
# it is required to know the direction of port connections
link_module_dec_def(d)
name_scope = NameScope.make_top(False)
for kw in HWT_KEYWORDS:
name_scope.register_name(kw, LanguageKeyword())
DiscoverDeclarations(name_scope).visit_HdlContext(d)
ResolveNames(name_scope).visit_HdlContext(d)
ser.visit_HdlContext(d)
res_str = buff.getvalue()
ref_file = os.path.join(ROOT, "ref", name + ref_file_suffix)
# with open(ref_file, "w", encoding="utf-8") as f:
# f.write(res_str)
with open(ref_file, encoding="utf-8") as f:
ref = f.read()
self.assertEqual(ref, res_str)
def checked_name(self, actualName, actualObj):
actualName = self.RE_MANY_UNDERSCORES.sub(r"_", actualName)
return NameScope.checked_name(self, actualName, actualObj)
def checked_name(self, actualName, actualObj):
actualName = self.RE_MANY_UNDERSCORES.sub(r"_", actualName)
if actualName[0] == "_":
actualName = "u" + actualName
return NameScope.checked_name(self, actualName, actualObj)