def run_IM_cosim(): # Initiate signals MAX_TIME = 1000000 clock = Signal(0) MR = Signal(0, delay=10) MW = Signal(0, delay=10) address = Signal(intbv(0, 0, 2**32), delay=10) WD = Signal(intbv(0, 0, 2**32), delay=10) pyData = Signal(intbv(0, 0, 2**32)) vData = Signal(intbv(0, 0, 2**32)) # Build driver instances clock_driver = clock_generator(clock, period=20) addr_driver = random_signal(clock, address, seed=1) WD_driver = random_signal(clock, WD, seed=2) MR_driver = pulse_generator(clock, MR, delay=2) MW_driver = pulse_generator(clock, MW, delay=3) py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD)) v_cosim = v_dm(clock, MR, MW, address, WD, vData) read_test = match_test_report(clock, vData, pyData, a_name="v:", b_name="py:") sim = Simulation(instances()) sim.run(MAX_TIME)
def run_ALU_cosim(): # Initiate signals MAX_TIME = 1000000 clock = Signal(0) reset = Signal(0) inA = Signal(intbv(0, 0, 2**32), delay=10) inB = Signal(intbv(0, 0, 2**32), delay=10) ALU_control = Signal(intbv(0, 0, 2**3), delay=10) pyData = Signal(intbv(0, 0, 2**32)) pyZero = Signal(intbv(0, 0, 2**32)) vData = Signal(intbv(0, 0, 2**32)) vZero = Signal(intbv(0, 0, 2**32)) # Build driver instances clock_driver = clock_generator(clock, period=20) control_driver = random_signal(clock, ALU_control, seed=1) A_rand = random_signal(clock, inA, seed=2) B_rand = random_signal(clock, inB, seed=3) reset_driver = pulse_generator(clock, reset) py_cosim = traceSignals( py_alu(clock, reset, inA, inB, ALU_control, pyData, pyZero)) v_cosim = v_alu(clock, reset, ALU_control, inA, inB, vData, vZero) read_test = match_test_report(clock, (vData, vZero), (pyData, pyZero), a_name="v:", b_name="py:") sim = Simulation(instances()) sim.run(MAX_TIME)
def run_hello_cosim(): clock = Signal(0) clock_driver = clock_generator(clock) din = Signal(intbv(val = 0, min = 0, max = 256)) rand = random_signal(clock, din) doutver = Signal(intbv(val = 0, min = 0, max = 256)) v_cosim = accumulator_cosim(clock, din, doutver) doutpy = Signal(modbv(val = 0, min = 0, max = 256)) py_cosim = Accumulator(clock, din, doutpy) match_t = match_test(clock, doutver, doutpy) sim = Simulation(clock_driver, rand, v_cosim, py_cosim, match_t) sim.run(1000)
def run_IM_cosim(): # Initiate signals MAX_TIME = 1000000 infile = INDEX_256 clock = Signal(0) address = Signal(intbv(0, 0, 2**32), delay=10) pyData = Signal(intbv(0, 0, 2**32)) vData = Signal(intbv(0, 0, 2**32)) # Build driver instances clock_driver = clock_generator(clock, period=20) addr_driver = random_signal(clock, address, seed=1) py_cosim = traceSignals(py_im(clock, address, pyData, infile)) v_cosim = v_im(clock, address, vData, infile) read_test = match_test_report(clock, vData, pyData, a_name="v:", b_name="py:") sim = Simulation(instances()) sim.run(MAX_TIME)
reset = Signal(0) ID_Hazard_lwstall = Signal(intbv(0, 0, 2**1)) ID_Hazard_branch = Signal(intbv(0, 0, 2**1)) #create drivers for signals reg_driver = traceSignals( id_ex(clock, reset, ID_Hazard_lwstall, ID_Hazard_branch, branch_in, MemRead_in, MemWrite_in, Jump_in, RegWrite_in, ALUSrc_in, ALUOp_in, RegDst_in, MemToReg_in, jump_addr_in, PC_Plus4_in, branch_addr_in, readA_in, readB_in, immi_sign_extended_in, RS_in, RT_in, RD_in, funct_in, RegWrite_out, branch_out, MemRead_out, MemWrite_out, Jump_out, ALUSrc_out, ALUOp_out, RegDst_out, MemToReg_out, jump_addr_out, PC_Plus4_out, branch_addr_out, readA_out, readB_out, immi_sign_extended_out, RS_out, RT_out, RD_out, funct_out)) clock_driver = clock_generator(clock) ID_Hazard_b_driver = random_signal(clock, ID_Hazard_branch) ID_Hazard_lw_driver = random_signal(clock, ID_Hazard_lwstall) branch_in_driver = random_signal(clock, branch_in) MemRead_driver = random_signal(clock, MemRead_in) MemWrite_driver = random_signal(clock, MemWrite_in) Jump_driver = random_signal(clock, Jump_in) RegWrite_driver = random_signal(clock, RegWrite_in) ALUSrc_driver = random_signal(clock, ALUSrc_in) ALUOp_driver = random_signal(clock, ALUOp_in) RegDst_driver = random_signal(clock, RegDst_in) MemToReg_driver = random_signal(clock, MemToReg_in) jump_addr_driver = random_signal(clock, jump_addr_in) PC_Plus4_driver = random_signal(clock, PC_Plus4_in) branch_addr_driver = random_signal(clock, branch_addr_in)
def run_RF_cosim(): # Initiate signals MAX_TIME = 10000 clock = Signal(0) reset = Signal(0, delay=10) writeSignal = Signal(0, delay=10) pyReadA = Signal(intbv(0, 0, 2**32)) pyReadB = Signal(intbv(0, 0, 2**32)) vReadA = Signal(intbv(0, 0, 2**32)) vReadB = Signal(intbv(0, 0, 2**32)) write = Signal(intbv(0, 0, 2**32), delay=10) rAddrA = Signal(intbv(0, 0, 2**5)) rAddrB = Signal(intbv(0, 0, 2**5)) wAddr = Signal(intbv(0, 0, 2**5), delay=10) pyregs = [] vregs = [] for i in range(0, 32): pyregs.append(Signal(intbv(0, 0, 2**32))) pyregs[i].driven = not pyregs[i].driven vregs.append(Signal(intbv(0, 0, 2**32))) vregs[i].driven = not vregs[i].driven # Build driver instances clock_driver = clock_generator(clock, period=20) reset_driver = pulse_generator(clock, reset, delay=30) write_driver = pulse_generator(clock, writeSignal, delay=2) wd_rand = random_signal(clock, write, seed=1) rdAddrA_rand = random_signal(clock, rAddrA, seed=2) rdAddrB_rand = random_signal(clock, rAddrB, seed=3) wAddr_rand = random_signal(clock, wAddr, seed=4) py_cosim = traceSignals( RegisterFile(pyReadA, pyReadB, write, rAddrA, rAddrB, wAddr, writeSignal, clock, reset, pyregs)) v_cosim = v_rf(vReadA, vReadB, write, rAddrA, rAddrB, wAddr, writeSignal, clock, reset, vregs) read_test = match_test_report(clock, (vReadA, vReadB), (pyReadA, pyReadB), a_name="v:", b_name="py:") reg_test = match_test_report(clock, vregs, pyregs, a_name="verilog", b_name="python") sim = Simulation(instances()) inp = "" help = 'Enter "run <cycles>" to run the simulation "print" to show the register files, or "quit" to exit.' prompt = "command: " print(help) while (inp != "quit"): inp = input(prompt) if inp == "show": for x, reg in enumerate(pyregs): print("py[%d]=%#x" % (x, reg.val), end=' ') print() for x, reg in enumerate(vregs): print(" v[%d]=%#x" % (x, reg.val), end=' ') print() if (pyregs == vregs): print("They match") else: print("They don't match") continue elif inp.startswith("run "): try: cycles = int(inp.split()[1].strip()) sim.run(cycles) continue except ValueError: pass elif inp != "quit": print(help)
def CPU(reset, regOut): clock = Signal(intbv(0, 0, 2**1)) clock_driver = clock_generator(clock) # Wires in the IF stage PC_out = Signal(intbv(0, 0, 2**32)) PC_plus4 = Signal(intbv(4, 0, 2**32)) instruction_out = Signal(intbv(0, 0, 2**32)) PO_write = Signal(intbv(0, 0, 2**1)) pcp4_driver = PC_Increment(clock, PC_out, PC_plus4) # Wires in the ID stage IF_ID_PC_plus4 = Signal(intbv(0, 0, 2**32)) IF_ID_instruction = Signal(intbv(0, 0, 2**32)) MEM_WB_RegisterRd = Signal(intbv(0, 0, 2**5)) reg_read_data_1 = Signal(intbv(0, 0, 2**32)) reg_read_data_2 = Signal(intbv(0, 0, 2**32)) immi_sign_extended = Signal(intbv(0, 0, 2**32)) # Jump within the ID stage BTA = Signal(intbv(0, 0, 2**32)) Jump_Address = Signal(intbv(0, 0, 2**32)) jump_base28 = Signal(intbv(0, 0, 2**28)) # Control Signal generation within the ID stage Jump = Signal(intbv(0, 0, 2**1)) Branch = Signal(intbv(0, 0, 2**1)) MemRead = Signal(intbv(0, 0, 2**1)) MemWrite = Signal(intbv(0, 0, 2**1)) ALUSrc = Signal(intbv(0, 0, 2**1)) RegWrite = Signal(intbv(0, 0, 2**1)) RegDst = Signal(intbv(0, 0, 2**2)) MemToReg = Signal(intbv(0, 0, 2**2)) ALUOp = Signal(intbv(0, 0, 2**3)) # ID Stage constants In3_jal_ra = Signal(intbv(31, 0, 2**5)) # Mux output wires first_alu_mux_3_to_1_out = Signal(intbv(0, 0, 2**32)) second_alu_mux_3_to_1_out = Signal(intbv(0, 0, 2**32)) third_alu_mux_2_to_1_out = Signal(intbv(0, 0, 2**32)) idEx_to_exMem_mux_2_to_1_out = Signal(intbv(0, 0, 2**5)) writeback_source_mux_3_to_1_out = Signal(intbv(0, 0, 2**32)) regDst_mux_3_to_1_out = Signal(intbv(0, 0, 2**5)) first_PC4_or_branch_mux_2_to_1_out = Signal(intbv(0, 0, 2**32)) second_jump_or_first_mux_2_to_1_out = Signal(intbv(0, 0, 2**32)) third_jr_or_second_mux_2_to_1_out = Signal(intbv(0, 0, 2**32)) h_RegWrite_out = Signal(intbv(0, 0, 2**1)) h_MemWrite_out = Signal(intbv(0, 0, 2**1)) # Wires for the LW hazard stall PCWrite = Signal(intbv(0, 0, 2**1)) # PC stop writing if PCWrite == 0 IF_ID_Write = Signal(intbv(1, 0, 2**1)) # IF/ID reg stops writing if IF_ID_Write == 0 ID_Flush_lwstall = Signal(intbv(0, 0, 2**1)) # Wires for jump/branch control PCSrc = Signal(intbv(0, 0, 2**1)) IF_Flush = Signal(intbv(0, 0, 2**1)) ID_Flush_Branch = Signal(intbv(0, 0, 2**1)) EX_Flush = Signal(intbv(0, 0, 2**1)) # Wires in the EX stage ID_EX_Jump = Signal(intbv(0, 0, 2**1)) ID_EX_Branch = Signal(intbv(0, 0, 2**1)) ID_EX_MemRead = Signal(intbv(0, 0, 2**1)) ID_EX_MemWrite = Signal(intbv(0, 0, 2**1)) ID_EX_ALUSrc = Signal(intbv(0, 0, 2**1)) ID_EX_RegWrite = Signal(intbv(0, 0, 2**1)) ALU_zero = Signal(intbv(0, 0, 2**1)) JRControl = Signal(intbv(0, 0, 2**1)) ID_EX_jump_addr = Signal(intbv(0, 0, 2**32)) ID_EX_branch_address = Signal(intbv(0, 0, 2**32)) ID_EX_PC_plus4 = Signal(intbv(0, 0, 2**32)) ID_EX_reg_read_data_1 = Signal(intbv(0, 0, 2**32)) ID_EX_reg_read_data_2 = Signal(intbv(0, 0, 2**32)) ID_EX_immi_sign_extended = Signal(intbv(0, 0, 2**32)) muxA_out = Signal(intbv(0, 0, 2**32)) muxB_out = Signal(intbv(0, 0, 2**32)) after_ALUSrc = Signal(intbv(0, 0, 2**32)) ALU_result = Signal(intbv(0, 0, 2**32)) after_shift = Signal(intbv(0, 0, 2**32)) ID_EX_RegDst = Signal(intbv(0, 0, 2**2)) ID_EX_MemtoReg = Signal(intbv(0, 0, 2**2)) out_to_ALU = Signal(intbv(0, 0, 2**2)) ID_EX_ALUOp = Signal(intbv(0, 0, 2**3)) ID_EX_RegisterRs = Signal(intbv(0, 0, 2**5)) ID_EX_RegisterRt = Signal(intbv(0, 0, 2**5)) ID_EX_RegisterRd = Signal(intbv(0, 0, 2**5)) EX_RegisterRd = Signal(intbv(0, 0, 2**5)) ID_EX_funct = Signal(intbv(0, 0, 2**6)) # Wires in the MEM stage EX_MEM_PC_plus_4 = Signal(intbv(0, 0, 2**32)) EX_MEM_RegisterRd = Signal(intbv(0, 0, 2**5)) EX_MEM_Branch = Signal(intbv(0, 0, 2**1)) EX_MEM_MemRead = Signal(intbv(0, 0, 2**1)) EX_MEM_MemWrite = Signal(intbv(0, 0, 2**1)) EX_MEM_Jump = Signal(intbv(0, 0, 2**1)) Branch_taken = Signal(intbv(0, 0, 2**1)) EX_MEM_ALU_zero = Signal(intbv(0, 0, 2**1)) EX_MEM_MemtoReg = Signal(intbv(0, 0, 2**2)) EX_MEM_RegWrite = Signal(intbv(0, 0, 2**1)) EX_MEM_jump_addr = Signal(intbv(0, 0, 2**32)) EX_MEM_branch_addr = Signal(intbv(0, 0, 2**32)) EX_MEM_ALU_result = Signal(intbv(0, 0, 2**32)) EX_MEM_reg_read_data_2 = Signal(intbv(0, 0, 2**32)) D_MEM_data = Signal(intbv(0, 0, 2**32)) # Wires in the WB Stage reg_write_data = Signal(intbv(0, 0, 2**32)) MEM_WB_PC_plus_4 = Signal(intbv(0, 0, 2**32)) MEM_WB_RegWrite = Signal(intbv(0, 0, 2**1)) MEM_WB_MemtoReg = Signal(intbv(0, 0, 2**2)) MEM_WB_D_MEM_read_data = Signal(intbv(0, 0, 2**32)) MEM_WB_D_MEM_read_addr = Signal(intbv(0, 0, 2**32)) # Wires for forwarding ForwardA = Signal(intbv(0, 0, 2**2)) ForwardB = Signal(intbv(0, 0, 2**2)) mem = [] branch_or_jump_taken = Signal(intbv(0, 0, 2**1)) PC_in = Signal(intbv(0, 0, 2**32)) Unit27 = PC_input_2_to_1(PC_plus4, third_jr_or_second_mux_2_to_1_out, branch_or_jump_taken, PC_in) Unit0 = program_counter(clock, reset, PC_out, PC_in, PCWrite) Unit1 = Instruction_Memory(clock, PC_out, instruction_out, "instructions.txt", mem) #IF stage: PC, IM, IF_ID_Reg # TODO: infile # se_driver = Sign_Extender(IF_ID_instruction(17,0), immi_sign_extended) Unit3 = if_id(clock, reset, instruction_out, IF_ID_instruction, PC_plus4, IF_ID_PC_plus4, IF_Flush, IF_ID_Write) #ID Stage: Control, Registers, branch_jump_cal, sign_extend, regDst_mux_3_to_1, #ID_EX_reg, Hazard_Detection_Unit Unit4 = control(IF_ID_instruction(32, 26), ALUSrc, RegDst, MemWrite, MemRead, Branch, Jump, MemToReg, RegWrite, ALUOp) Unit5 = regDst_mux_3_to_1(IF_ID_instruction(21,16), IF_ID_instruction(26,21), In3_jal_ra, RegDst, regDst_mux_3_to_1_out) Unit25 = hazard_unit(ID_EX_MemRead, ID_EX_RegisterRt, IF_ID_instruction(26,21), IF_ID_instruction(21,16), ID_Flush_lwstall, PCWrite, IF_ID_Write) Unit6 = hazard_stall_mux_2_to_1(RegWrite, MemWrite, ID_Flush_lwstall, h_RegWrite_out, h_MemWrite_out) Unit28 = writeback_source_mux_3_to_1(MEM_WB_D_MEM_read_addr, MEM_WB_D_MEM_read_data, MEM_WB_PC_plus_4, MEM_WB_MemtoReg, writeback_source_mux_3_to_1_out) Unit7 = RegisterFile(reg_read_data_1, reg_read_data_2, writeback_source_mux_3_to_1_out, IF_ID_instruction(26, 21), IF_ID_instruction(21, 16), regDst_mux_3_to_1_out, MEM_WB_RegWrite, clock, reset, regOut) Unit8 = branch_calculator(immi_sign_extended, IF_ID_PC_plus4, BTA) Unit9 = jump_calculator(IF_ID_instruction, IF_ID_PC_plus4, Jump_Address) Unit24 = id_ex(clock, reset, ID_Flush_lwstall, ID_Flush_Branch, Branch, MemRead, MemWrite, Jump, RegWrite, ALUSrc, ALUOp, RegDst, MemToReg, Jump_Address, BTA, IF_ID_PC_plus4, reg_read_data_1, reg_read_data_2, immi_sign_extended, IF_ID_instruction(26,21), IF_ID_instruction(21,16), IF_ID_instruction(16,11), IF_ID_instruction(6,0), ID_EX_RegWrite, ID_EX_Branch, ID_EX_MemRead, ID_EX_MemWrite, ID_EX_Jump, ID_EX_ALUSrc, ID_EX_ALUOp, ID_EX_RegDst, ID_EX_MemtoReg, ID_EX_jump_addr, ID_EX_branch_address, ID_EX_PC_plus4, ID_EX_reg_read_data_1, ID_EX_reg_read_data_2, ID_EX_immi_sign_extended, ID_EX_RegisterRs, ID_EX_RegisterRt, ID_EX_RegisterRd, ID_EX_funct) #EX Stage: Unit11 = alu_control(ID_EX_ALUOp, ID_EX_funct, out_to_ALU) Unit12 = JR_Control(ID_EX_ALUOp, ID_EX_funct, JRControl) #ID_EX_RegRs, ID_EX_RegRt, EX_MEM_RegRd, EX_MEM_RegWrite, MEM_WB_RegRd, MEM_WB_RegWrite, Mux_ForwardA, Mux_ForwardB Unit13 = ForwardingUnit(ID_EX_RegisterRs, ID_EX_RegisterRt, EX_MEM_RegisterRd, MEM_WB_RegisterRd, MEM_WB_RegWrite, EX_MEM_RegWrite, ForwardA, ForwardB) Unit14 = first_alu_mux_3_to_1(ID_EX_reg_read_data_1, EX_MEM_reg_read_data_2, MEM_WB_D_MEM_read_data, ForwardA, first_alu_mux_3_to_1_out) Unit15 = second_alu_mux_3_to_1(ID_EX_reg_read_data_2, EX_MEM_reg_read_data_2, MEM_WB_D_MEM_read_data, ForwardB, second_alu_mux_3_to_1_out) Unit16 = third_alu_mux_2_to_1(second_alu_mux_3_to_1_out, immi_sign_extended, ALUSrc, third_alu_mux_2_to_1_out) Unit10 = alu(clock, reset, first_alu_mux_3_to_1_out, third_alu_mux_2_to_1_out, out_to_ALU, ALU_result, ALU_zero) Unit17 = idEx_to_exMem_mux_2_to_1(ID_EX_RegisterRd, ID_EX_RegisterRt, ID_EX_RegDst, idEx_to_exMem_mux_2_to_1_out) Unit18 = ex_mem(clock, reset, EX_Flush, ID_EX_RegWrite, ID_EX_MemtoReg, ID_EX_Branch, ID_EX_MemRead, ID_EX_MemWrite, ID_EX_Jump, ID_EX_jump_addr, ID_EX_branch_address, ALU_zero, ALU_result, second_alu_mux_3_to_1_out, idEx_to_exMem_mux_2_to_1_out, ID_EX_PC_plus4, EX_MEM_RegWrite, EX_MEM_MemtoReg, EX_MEM_Branch, EX_MEM_MemRead, EX_MEM_MemWrite, EX_MEM_Jump, EX_MEM_jump_addr, EX_MEM_branch_addr, EX_MEM_ALU_zero, EX_MEM_ALU_result, EX_MEM_reg_read_data_2, EX_MEM_RegisterRd, EX_MEM_PC_plus_4) #Mem Stage: Unit19 = Data_Memory(clock, EX_MEM_ALU_result, EX_MEM_MemWrite, EX_MEM_MemRead, D_MEM_data, EX_MEM_reg_read_data_2) Unit26 = branch_or_jump_taken_flush(EX_MEM_Branch, EX_MEM_Jump, EX_MEM_ALU_zero, IF_Flush, ID_Flush_Branch, EX_Flush, branch_or_jump_taken) Unit20 = mem_wb(clock, reset, EX_MEM_RegWrite, EX_MEM_MemtoReg, D_MEM_data, EX_MEM_ALU_result, EX_MEM_RegisterRd, EX_MEM_PC_plus_4, MEM_WB_D_MEM_read_data, MEM_WB_D_MEM_read_addr, MEM_WB_RegisterRd, MEM_WB_RegWrite, MEM_WB_MemtoReg, MEM_WB_PC_plus_4) branch_taken = Signal(intbv(0, 0, 2**1)) branch_checker = isBranch(ALU_zero, Branch, branch_taken) Unit21 = first_PC4_or_branch_mux_2_to_1(ID_EX_PC_plus4, BTA, branch_taken, first_PC4_or_branch_mux_2_to_1_out) Unit22 = second_jump_or_first_mux_2_to_1(first_PC4_or_branch_mux_2_to_1_out, Jump_Address, Jump, second_jump_or_first_mux_2_to_1_out) Unit23 = third_jr_or_second_mux_2_to_1(second_jump_or_first_mux_2_to_1_out, regOut[31], JRControl, third_jr_or_second_mux_2_to_1_out) return instances()