def _config(self):
self.ACASCREG = Param(1)
self.ADREG = Param(1)
self.ALUMODEREG = Param(1)
self.AREG = Param(1)
self.AUTORESET_PATDET = Param("NO_RESET")
self.A_INPUT = Param("DIRECT")
self.BCASCREG = Param(1)
self.BREG = Param(1)
self.B_INPUT = Param("DIRECT")
self.CARRYINREG = Param(1)
self.CARRYINSELREG = Param(1)
self.CREG = Param(1)
self.DREG = Param(1)
self.INMODEREG = Param(1)
self.IS_ALUMODE_INVERTED = Param(Bits(4).from_py(0b0000))
self.IS_CARRYIN_INVERTED = Param(BIT.from_py(0b0))
self.IS_CLK_INVERTED = Param(BIT.from_py(0b0))
self.IS_INMODE_INVERTED = Param(Bits(5).from_py(0b00000))
self.IS_OPMODE_INVERTED = Param(Bits(7).from_py(0b0000000))
self.MASK = Param(Bits(48).from_py(0x3fffffffffff))
self.MREG = Param(1)
self.OPMODEREG = Param(1)
self.PATTERN = Param(Bits(48).from_py(0x000000000000))
self.PREG = Param(1)
self.SEL_MASK = Param("MASK")
self.SEL_PATTERN = Param("PATTERN")
self.USE_DPORT = Param("FALSE")
self.USE_MULT = Param("MULTIPLY")
self.USE_PATTERN_DETECT = Param("NO_PATDET")
self.USE_SIMD = Param("ONE48")
class AxiS_FrameJoin_3x_in_1B_on_5B_TC(AxiS_FrameJoin_1x_2B_TC):
D_B = 5
T = HStruct(
(HStream(Bits(8 * 1), (1, inf), [0]), "frame0"),
(HStream(Bits(8 * 1), (1, inf), [0]), "frame1"),
(HStream(Bits(8 * 1), (1, inf), [0]), "frame2"),
)
def makeTestbenchTemplate(unit: Unit, name: str=None):
"""
:param unit: synthesized unit
:return: (entity, arch, context) of testbench
"""
if name is None:
name = unit._name + "_tb"
entity = Entity(name)
arch = Architecture(entity)
arch.components.append(unit._entity)
arch.componentInstances.append(unit._entity)
nl = RtlNetlist()
ctx = {}
for p in unit._entity.ports:
t = p._dtype
if isinstance(t, Bits) and not t == BIT:
t = Bits(t.bit_length(), signed=t.signed,
forceVector=t.forceVector)
s = RtlSignal(nl, p.name, t, t.fromPy(0))
ctx[p._interface] = s
p.connectSig(s)
arch.variables.extend(ctx.values())
return entity, arch, ctx
def HdlType_bits(cls, typ: Bits, ctx, declaration=False):
isVector = typ.force_vector or typ.bit_length() > 1
nameBuff = []
sigType = ctx.signalType
if sigType is SIGNAL_TYPE.PORT:
pass
elif sigType is SIGNAL_TYPE.REG:
nameBuff.append("reg")
elif sigType is SIGNAL_TYPE.WIRE:
nameBuff.append("wire")
else:
raise NotImplementedError()
if typ.signed:
nameBuff.append("signed")
w = typ.bit_length()
if not isVector:
pass
elif isinstance(w, int):
nameBuff.append("[%d:0]" % (w - 1))
else:
nameBuff.append("[%s- 1:0]" % cls.Value(w, ctx))
return " ".join(nameBuff)
def __init__(self,
avalon_mm: AvalonMM,
parent=None,
clk=None,
allow_unaligned_addr=False):
"""
:param clk: clk which should this memory use in simulation
(if None the clk associated with an interface is used)
:param avalon_mm: avalon_mm (AvalonMM master) interface to listen on
:param parent: parent instance of this memory, memory will operate
with same memory as parent one
:attention: memories are commiting into memory in "data" property
after transaction is complete
"""
DW = avalon_mm.DATA_WIDTH
self.allow_unaligned_addr = allow_unaligned_addr
SimRam.__init__(self, DW // 8, parent=parent)
self.allMask = mask(self.cellSize)
self.word_t = Bits(self.cellSize * 8)
if clk is None:
clk = avalon_mm._getAssociatedClk()
self.bus = avalon_mm
self.clk = clk
self._registerOnClock()
self.wPending = deque()
def IndexOps():
t = Bits(8)
n = RtlNetlist()
s_in = n.sig("s_in", t)
s_out = n.sig("s_out", t)
s_in2 = n.sig("s_in2", t)
s_out2 = n.sig("s_out2", t)
s_in3 = n.sig("s_in3", Bits(16))
s_out3 = n.sig("s_out3", t)
s_in4a = n.sig("s_in4a", t)
s_in4b = n.sig("s_in4b", t)
s_out4 = n.sig("s_out4", Bits(16))
s_out(s_in[4:]._concat(vec(2, 4)))
s_out2[4:](s_in2[4:])
s_out2[:4](s_in2[:4])
s_out3(s_in3[8:])
s_out4[8:](s_in4a)
s_out4[(8 + 8):8](s_in4b)
interf = [
s_in, s_out, s_in2, s_out2, s_in3, s_out3, s_in4a, s_in4b, s_out4
]
return n, interf
def setUpCrc(self,
poly,
dataWidth=None,
refin=None,
refout=None,
initval=None,
finxor=None,
use_mask=False,
is_bigendian=False):
if dataWidth is None:
dataWidth = poly.WIDTH
u = self.u = Crc()
u.setConfig(poly)
if initval is not None:
u.INIT = Bits(poly.WIDTH).from_py(initval)
u.DATA_WIDTH = dataWidth
if refin is not None:
u.REFIN = refin
if refout is not None:
u.REFOUT = refout
if finxor is not None:
u.XOROUT = Bits(poly.WIDTH).from_py(finxor)
u.MASK_GRANULARITY = 8 if use_mask else None
u.IN_IS_BIGENDIAN = is_bigendian
self.compileSimAndStart(u)
return u
def as_hdl_HdlType_bits(self, typ: Bits, declaration=False):
isVector = typ.force_vector or typ.bit_length() > 1
sigType = self.signalType
if typ == INT:
t = HdlValueId("int", obj=int)
elif sigType is SIGNAL_TYPE.PORT_WIRE:
t = HdlTypeAuto
elif sigType is SIGNAL_TYPE.REG or sigType is SIGNAL_TYPE.PORT_REG:
t = HdlValueId("reg", obj=LanguageKeyword())
elif sigType is SIGNAL_TYPE.WIRE:
t = HdlValueId("wire", obj=LanguageKeyword())
else:
raise ValueError(sigType)
if typ.signed is None:
is_signed = None
else:
is_signed = self.as_hdl_int(int(typ.signed))
if isVector:
w = typ.bit_length()
assert isinstance(w, int) or (isinstance(w, RtlSignal)
and w._const), w
w = hdl_downto(self.as_hdl(w - 1), self.as_hdl_int(0))
else:
w = None
return HdlOp(HdlOpType.PARAMETRIZATION, [t, w, is_signed])
def setUpCrc(self,
poly,
dataWidth=None,
refin=None,
refout=None,
initval=None,
finxor=None,
bigendian=False):
if dataWidth is None:
dataWidth = poly.WIDTH
u = self.u = CrcComb()
u.setConfig(poly)
u.DATA_WIDTH = dataWidth
if initval is not None:
u.INIT = Bits(poly.WIDTH).from_py(initval)
if refin is not None:
u.REFIN = refin
if refout is not None:
u.REFOUT = refout
if finxor is not None:
u.XOROUT = Bits(poly.WIDTH).from_py(finxor)
u.IN_IS_BIGENDIAN = bigendian
self.compileSimAndStart(u)
return u
def _impl(self):
concat_type = Bits(bit_length=self.width * 2 - 1, force_vector=True)
concat_inputs = [
self._sig(name=f"concat_inputs_{i}", dtype=concat_type)
for i in range(15)
]
data_type = Bits(bit_length=15, force_vector=True)
data_a = self._sig(name="data_a", dtype=data_type, def_val=0)
data_b = self._sig(name="data_b", dtype=data_type, def_val=0)
non_zero_a = self._sig(name="non_zero_a", dtype=Bits(1))
non_zero_b = self._sig(name="non_zero_b", dtype=Bits(1))
xor_signal = self._sig(name="xor_signal", dtype=Bits(1))
data_a[self.width - 1:](self.param_a[self.width - 1:])
data_b[self.width - 1:](self.param_b[self.width - 1:])
for i in range(15):
self.concat_units[i].param_a(data_a)
self.concat_units[i].param_b(data_b)
concat_inputs[i](self.concat_units[i].output)
fourth_sum = self.__calc_tree_adders(concat_inputs)
If(data_a._eq(0), non_zero_a(0)).Else(non_zero_a(1))
If(data_b._eq(0), non_zero_b(0)).Else(non_zero_b(1))
xor_signal(self.param_a[self.width - 1] ^ self.param_b[self.width - 1])
self.product[self.width - 1](xor_signal & non_zero_a & non_zero_b)
self.product[self.width - 1:](
fourth_sum[self.lower_output_bit + self.width -
1:self.lower_output_bit])
def _impl(self):
self.signalLoop.din(self.signalIn)
self.regCntrlOut(self.regCntrlLoop.dout)
self.vldSyncedOut(self.vldSyncedLoop.dout)
self.bramOut(self.bramLoop.dout)
def configEp(ep):
ep._updateParamsFrom(self)
rltSig10 = self._sig("sig", Bits(self.DATA_WIDTH), def_val=10)
interfaceMap = IntfMap([
(rltSig10, "rltSig10"),
(self.signalLoop.dout, "signal"),
(self.regCntrlLoop.din, "regCntrl"),
(self.vldSyncedLoop.din, "vldSynced"),
(self.bramLoop.din, "bram"),
(Bits(self.DATA_WIDTH), None),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
axiLiteConv.decoded.vldSynced.din(None)
propagateClkRstn(self)
def test_read(self, n=4 * (512 // 32), n2=2, magic=99, randomize=False):
u = self.u
in_addr_step = u.DATA_WIDTH // 8
out_addr_step = u.OUT_DATA_WIDTH // 8
in_words_in_out_word = out_addr_step // in_addr_step
expected = []
for _ in range(n2):
for in_i in range(n):
u.s.ar._ag.data.append((in_i * in_addr_step, PROT_DEFAULT))
in_w = magic + in_i
expected.append(in_w)
m = Axi4LiteSimRam(u.m)
in_t = Bits(u.DATA_WIDTH)[in_words_in_out_word]
out_t = Bits(u.OUT_DATA_WIDTH)
for out_w_i, out_w in enumerate(
grouper(in_words_in_out_word, expected, padvalue=0)):
w = in_t.from_py(out_w)._reinterpret_cast(out_t)
m.data[out_w_i] = w
t = n2 * n
if randomize:
self.randomize_all()
t *= 5
self.runSim((t + 10) * CLK_PERIOD)
self.assertValSequenceEqual(u.s.r._ag.data, [(v, 0) for v in expected])
def filter(self, name, sig):
"""attempt to remove glitches"""
filter0 = self._reg(name + "_filter0", dtype=Bits(2), defVal=0)
filter0(filter0[0]._concat(sig))
# let filter_cnt to be shared between filters
try:
filter_clk_cntr = self.filter_clk_cntr
except AttributeError:
filter_clk_cntr = self.filter_clk_cntr = self._reg("filter_clk_cntr",
Bits(self.CLK_CNTR_WIDTH),
defVal=self.clk_cnt_initVal)
If(filter_clk_cntr._eq(0),
filter_clk_cntr(self.clk_cnt_initVal)
).Else(
filter_clk_cntr(filter_clk_cntr - 1)
)
filter1 = self._reg(name + "_filter1", dtype=Bits(3), defVal=0b111)
If(filter_clk_cntr._eq(0),
filter1(Concat(filter1[2:], filter0[1]))
)
filtered = ((filter1[2] & filter1[1]) |
(filter1[2] & filter1[0]) |
(filter1[1] & filter1[0]))
return filtered
def __mul__(self, other):
Bits = self._dtype.__class__
other = toHVal(other)
if not isinstance(other._dtype, Bits):
raise TypeError(other)
if areValues(self, other):
return self._mul__val(other)
else:
myT = self._dtype
if self._dtype.signed is None:
self = self._unsigned()
if isinstance(other._dtype, Bits):
s = other._dtype.signed
if s is None:
other = other._unsigned()
else:
raise TypeError("%r %r %r" % (self, AllOps.MUL, other))
if other._dtype == INT:
res_w = myT.bit_length() * 2
res_sign = self._dtype.signed
else:
res_w = myT.bit_length() + other._dtype.bit_length()
res_sign = self._dtype.signed or other._dtype.signed
subResT = Bits(res_w, signed=res_sign)
o = Operator.withRes(AllOps.MUL, [self, other], subResT)
resT = Bits(res_w, signed=myT.signed)
return o._auto_cast(resT)
def _concat(self, other):
"""
Concatenate this with other to one wider value/signal
"""
w = self._dtype.bit_length()
try:
other._dtype.bit_length
except AttributeError:
raise TypeError("Can not concat Bits and", other._dtype)
if areValues(self, other):
return self._concat__val(other)
else:
w = self._dtype.bit_length()
other_w = other._dtype.bit_length()
resWidth = w + other_w
Bits = self._dtype.__class__
resT = Bits(resWidth, signed=self._dtype.signed)
# is instance of signal
if isinstance(other, InterfaceBase):
other = other._sig
if isinstance(other._dtype, Bits):
if other._dtype.signed is not None:
other = other._vec()
elif other._dtype == BOOL:
other = other._auto_cast(BIT)
else:
raise TypeError(other._dtype)
if self._dtype.signed is not None:
self = self._vec()
return Operator.withRes(AllOps.CONCAT, [self, other], resT)\
._auto_cast(Bits(resWidth,
signed=self._dtype.signed))
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld, connect(cEn.dout.data, en, fit=True))
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld, connect(cLen.dout.data, _len, fit=True))
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld, connect(cLen.dout.data, cntr, fit=True)).Else(
If(out.ready & en,
If(cntr._eq(0), cntr(_len)).Else(cntr(cntr - 1))))
def test_HTypeFromIntfMap_StructArray(self):
DATA_WIDTH = 32
t = HTypeFromIntfMap(
IntfMap([
regCntr("a", DATA_WIDTH),
(Bits(4 * DATA_WIDTH), None),
([
IntfMap([
vldSynced("d", DATA_WIDTH),
sig("e", DATA_WIDTH),
(Bits(DATA_WIDTH * 2), None),
sig("f", DATA_WIDTH),
]) for _ in range(4)], "ds")
]))
_t = Bits(DATA_WIDTH)
self.assertEqual(t,
HStruct(
(_t, "a"),
(Bits(4 * DATA_WIDTH), None),
(HStruct(
(_t, "d"),
(_t, "e"),
(Bits(2 * DATA_WIDTH), None),
(_t, "f"),
)[4], "ds", HStructFieldMeta(split=True)),
))
def split_select(self, outputSelSignalOrSequence, noOfOutputs):
"""
Create a demultiplexer with number of outputs specified by noOfOutputs
:param noOfOutputs: number of outputs of multiplexer
:param outputSelSignalOrSequence: handshaked interface (onehot encoded)
to control selected output or sequence of output indexes
which should be used (will be repeated)
"""
if not self.master_to_slave:
assert len(self.end) == noOfOutputs, self.end
def setChCnt(u):
u.OUTPUTS = noOfOutputs
self._genericInstance(self.SplitSelectCls, 'select', setChCnt)
if isinstance(outputSelSignalOrSequence, Handshaked):
self.lastComp.selectOneHot(outputSelSignalOrSequence)
else:
seq = outputSelSignalOrSequence
t = Bits(self.lastComp.selectOneHot.data._dtype.bit_length())
size = len(seq)
ohIndexes = map(lambda x: 1 << x, seq)
indexes = self.parent._sig(self.name + "split_seq",
t[size],
def_val=ohIndexes)
actual = self.parent._reg(self.name + "split_seq_index",
Bits(size.bit_length()), 0)
iin = self.lastComp.selectOneHot
iin.data(indexes[actual])
iin.vld(1)
If(iin.rd,
If(actual._eq(size - 1), actual(0)).Else(actual(actual + 1)))
return self
def _get(self, numberOfBits: int, doCollect: bool):
"""
:param numberOfBits: number of bits to get from actual possition
:param doCollect: if False output is not collected just iterator moves
in structure
"""
if not isinstance(numberOfBits, int):
numberOfBits = int(numberOfBits)
while self.actuallyHave < numberOfBits:
# accumulate while not has enought
try:
f = next(self.it)
except StopIteration:
if self.fillup and self.actual is not None:
break
else:
raise NotEnoughtBitsErr()
thisFieldLen = f._dtype.bit_length()
if self.actual is None:
if not doCollect and thisFieldLen <= numberOfBits:
numberOfBits -= thisFieldLen
else:
self.actual = f
self.actuallyHave = thisFieldLen
else:
if not doCollect and self.actuallyHave < numberOfBits:
self.actuallyHave = thisFieldLen
self.actual = f
else:
self.actuallyHave += thisFieldLen
self.actual = f._concat(self.actual)
# slice out from actual
actual = self.actual
actualOffset = self.actualOffset
if self.actuallyHave < numberOfBits:
assert self.fillup
if doCollect:
t = self.actual._dtype
fillupW = numberOfBits - self.actuallyHave
padding_t = Bits(fillupW, signed=t.signed, negated=t.negated)
padding = padding_t.fromPy(None)
actual = padding._concat(actual)
self.actuallyHave = 0
# update about what was taken
self.actuallyHave -= numberOfBits
self.actualOffset += numberOfBits
if self.actuallyHave == 0:
self.actual = None
self.actualOffset = 0
if doCollect:
if numberOfBits == 1:
return actual[actualOffset]
else:
return actual[(actualOffset + numberOfBits):actualOffset]
def as_hdl_HdlType_bits(self, typ: Bits, declaration=False):
if declaration:
raise NotImplementedError()
if typ == BOOL:
return self.BOOLEAN
if typ == INT:
return self.INTEGER
bitLength = typ.bit_length()
w = typ.bit_length()
isVector = typ.force_vector or bitLength > 1
if typ.signed is None:
if isVector:
name = self.STD_LOGIC_VECTOR
else:
return self.STD_LOGIC
elif typ.signed:
name = self.SIGNED
else:
name = self.UNSIGNED
return HdlOp(HdlOpType.CALL, [
name,
HdlOp(HdlOpType.DOWNTO, [
self.as_hdl(w - 1),
self.as_hdl_int(0)
])])
def _impl(self):
propagateClkRstn(self)
self.regsConventor.bus(self.cntrlBus)
axi = self.axi
# disable read channel
c(0, *where(axi.ar._interfaces, lambda x: x is not axi.ar.ready))
axi.r.ready(0)
axi.b.ready(1) # we do ignore write confirmations
st_t = HEnum("state_type",
["fullIdle", "writeAddr", "writeData", "writeDataLast"])
onoff = self._reg("on_off_reg", defVal=0)
baseAddr = self._reg("baseAddr_reg", Bits(self.ADDR_WIDTH), 0)
st = self._reg("state_reg", st_t, st_t.fullIdle)
actualAddr = self._reg("actualAddr_reg", Bits(self.ADDR_WIDTH))
lenRem = self._reg("lenRem_reg",
Bits(int(self.DATA_LEN).bit_length() + 1),
self.DATA_LEN)
actualLenRem = self._reg("actualLenRem_reg", axi.aw.len._dtype)
self.connectRegisters(st, onoff, baseAddr)
self.axiWAddrHandler(st, baseAddr, actualAddr, lenRem)
self.mainFsm(st, onoff, lenRem, actualLenRem)
self.dataWFeed(st, lenRem, actualLenRem)
def test_HTypeFromIntfMap_ArrayOfStructs(self):
DATA_WIDTH = 32
t = HTypeFromIntfMap(
IntfMap([
regCntr("a", DATA_WIDTH),
(Bits(4 * DATA_WIDTH), None),
([IntfMap([
vldSynced("c", DATA_WIDTH),
vldSynced("d", DATA_WIDTH)
]) for _ in range(4)], "ds")
]))
_t = Bits(DATA_WIDTH)
_t2 = HStruct(
(_t, "c"),
(_t, "d")
)
t2 = HStruct(
(_t, "a"),
(Bits(4 * DATA_WIDTH), None),
(_t2[4], "ds", HStructFieldMeta(split=True)),
)
self.assertEqual(t, t2)
def __setitem__(self, index, value):
"""
this []= operator can not be called in desing description, it can be only used to update HValues
"""
if not isinstance(self, HValue):
raise TypeError(
"To assign a member of hdl arrray/vector/list/... use a[index](val) instead of a[index] = val"
)
# convert index to hSlice or hInt
if isinstance(index, HValue):
index = index
elif isinstance(index, slice):
length = self._dtype.bit_length()
index = slice_to_SLICE(index, length)
if not index._is_full_valid():
raise ValueError("invalid index", index)
else:
index = hInt(index)
# convert value to bits of length specified by index
if index._dtype == SLICE:
Bits = self._dtype.__class__
itemT = Bits(index._size())
else:
itemT = BIT
if isinstance(value, HValue):
value = value._auto_cast(itemT)
else:
value = itemT.from_py(value)
return Bits3val.__setitem__(self, index, value)
def test_write(self, n=4 * (512 // 32), n2=2, magic=99, randomize=False):
u = self.u
in_addr_step = u.DATA_WIDTH // 8
out_addr_step = u.OUT_DATA_WIDTH // 8
in_words_in_out_word = out_addr_step // in_addr_step
w_data = []
for _ in range(n2):
for in_i in range(n):
u.s.aw._ag.data.append((in_i * in_addr_step, PROT_DEFAULT))
in_w = magic + in_i
w_data.append(in_w)
u.s.w._ag.data.extend([(d, mask(in_addr_step)) for d in w_data])
m = Axi4LiteSimRam(u.m)
in_t = Bits(u.DATA_WIDTH)[n]
out_t = Bits(u.OUT_DATA_WIDTH)[n // in_words_in_out_word]
t = n2 * n
if randomize:
self.randomize_all()
t *= 5
self.runSim((t + 10) * CLK_PERIOD)
v = m.getArray(0x0, out_addr_step, n // in_words_in_out_word)
v = out_t.from_py(v)._reinterpret_cast(in_t)
self.assertValSequenceEqual(v, w_data[n * (n2 - 1):])
def translate_addr_signal(self, mem_map, sig_in, sig_out):
cases = []
AW = sig_in._dtype.bit_length()
for (offset_in, size, offset_out) in mem_map:
in_is_aligned = offset_in % size == 0 and isPow2(size)
out_is_aligned = offset_out % size == 0 and isPow2(size)
if in_is_aligned:
L = (size - 1).bit_length()
en_sig = sig_in[:L]._eq(offset_in >> L)
_sig_in = sig_in[L:]
if out_is_aligned:
addr_drive = Concat(
Bits(AW - L).from_py(offset_out), _sig_in)
else:
addr_drive = Concat(Bits(AW - L).from_py(0),
_sig_in) + offset_out
else:
en_sig = inRange(sig_in, offset_in, offset_in + size)
if offset_in == offset_out:
addr_drive = sig_in
elif offset_in < offset_out:
addr_drive = sig_in + (offset_out - offset_in)
else:
# offset_in > offset_out:
addr_drive = sig_in - (offset_in - offset_out)
cases.append((en_sig, sig_out(addr_drive)))
SwitchLogic(cases, default=sig_out(sig_in))
def test_BitsFromIncompatibleType(self):
t = Bits(2)
with self.assertRaises(ValueError):
t.fromPy("a1")
with self.assertRaises(TypeError):
t.fromPy(object())
def _impl(self) -> None:
start = self._sig("start")
part_res_t = Bits(self.DATA_WIDTH)
# High-order n bits of product
a = self._reg("a", part_res_t)
# multiplicand
m = self._reg("m", part_res_t)
# Initially holds multiplier, ultimately holds low-order n bits of product
q = self._reg("q", part_res_t)
# previous bit 0 of q
q_1 = self._reg("q_1")
din = self.dataIn
dout = self.dataOut
counter = self._reg(
"counter",
Bits(log2ceil(self.DATA_WIDTH + 1), signed=False),
def_val=0)
done = counter._eq(0)
waitinOnConsumer = self._reg("waitinOnConsumer", def_val=0)
add = rename_signal(self, (a + m)._signed(), "add")
sub = rename_signal(self, (a - m)._signed(), "sub")
If(start,
a(0),
m(din.a),
q(din.b),
q_1(0),
counter(self.DATA_WIDTH),
).Elif(~done,
Switch(Concat(q[0], q_1))
.Case(0b01,
# add multiplicand to left half of product
a(add >> 1),
q(Concat(add[0], q[:1])),
).Case(0b10,
# substract multiplicand from left half of product
a(sub >> 1),
q(Concat(sub[0], q[:1])),
).Default(
a(a._signed() >> 1),
q(Concat(a[0], q[:1])),
),
q_1(q[0]),
counter(counter - 1)
)
If(start,
waitinOnConsumer(1)
).Elif(done & dout.rd,
waitinOnConsumer(0),
)
dout.data(Concat(a, q)._vec())
dout.vld(done & waitinOnConsumer)
start(din.vld & done & ~waitinOnConsumer)
din.rd(done & ~waitinOnConsumer)
def test_8b_xor(self, t=int8_t):
ut = Bits(t.bit_length())
m = t.all_mask()
v = t.fromPy(-1)
self.assertEqual(v ^ ut.fromPy(m), 0)
self.assertEqual(v ^ ut.fromPy(0), -1)
self.assertEqual(v ^ ut.fromPy(1), -2)
def test_8b_xor(self, t=int8_t):
ut = Bits(t.bit_length())
m = t.all_mask()
v = t.fromPy(-1)
self.assertEqual(v ^ ut.fromPy(m), 0)
self.assertEqual(v ^ ut.fromPy(0), -1)
self.assertEqual(v ^ ut.fromPy(1), -2)
def test_BitsConcatIncompatibleType(self):
t = Bits(1)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v._concat(hInt(2))
p = Param(1)
with self.assertRaises(TypeError):
v._concat(p)
def test_BitsConcatIncompatibleType(self):
t = Bits(1)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v._concat(hInt(2))
p = Param(1)
with self.assertRaises(TypeError):
v._concat(p)
class Mdio(Interface):
"""
Management Data Input/Output (MDIO), also known as Serial Management Interface (SMI)
or Media Independent Interface Management (MIIM), is a serial bus defined
for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface,
:note: Typical clock frequency is 2.5 MHz
* MDIO packet format: <PRE><ST><OP><PA><RA><TA><D>
* PRE: 32b preamble
* ST: 2b start field
* OP: 2b operation code
* PA: 5b PHY address
* RA: 5b register address
* TA: 2b turn arround
* D 16b data
:note: When data is being written to the slave, the master writes '10' to the MDIO line.
When data is being read, the master releases the MDIO line and slave sets the second bit to 1.
.. hwt-autodoc::
"""
# http://ww1.microchip.com/downloads/en/devicedoc/00002165b.pdf
PRE_W = 32
ST_W = 2
OP_W = 2
PA_W = 5
RA_W = 5
TA_W = 2
ADDR_BLOCK_W = ST_W + OP_W + PA_W + RA_W
D_W = 16
PRE = Bits(PRE_W).from_py(mask(PRE_W))
ST = Bits(ST_W).from_py(0b01)
TA = Bits(TA_W).from_py(0b10)
class OP:
READ = 0b10
WRITE = 0b01
DEFAULT_FREQ = int(2.5e6)
def _config(self):
self.FREQ = Param(self.DEFAULT_FREQ)
def _declr(self):
self.c = Clk()
self.c.FREQ = self.FREQ
with self._associated(clk=self.c):
self.io = TristateSig()
def _initSimAgent(self, sim: HdlSimulator):
self._ag = MdioAgent(sim, self)
def _getIpCoreIntfClass(self):
return IP_mdio
def test_BitsIndexOnSingleBit(self):
t = Bits(1)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v[0]
t = Bits(1, forceVector=True)
v = t.fromPy(1)
self.assertEqual(v[0], hBit(1))
def _impl(self):
internA = self._sig("internA", Bits(2))
internB = self._sig("internB", Bits(2))
internA(self.a[2:])
internB(self.a[:2])
self.b[2:](internA)
self.b[:2](internB)
def test_8b_cast(self, t=int8_t):
w = t.bit_length()
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1)._auto_cast(ut)), mask(w))
self.assertEqual(int(t.fromPy(-1)._unsigned()), mask(w))
self.assertEqual(int(t.fromPy(-1)._vec()), mask(w))
self.assertEqual(int(t.fromPy(1)._auto_cast(ut)), 1)
self.assertEqual(int(t.fromPy(0)._auto_cast(ut)), 0)
self.assertEqual(int(ut.fromPy(1)._auto_cast(t)), 1)
self.assertEqual(int(ut.fromPy(mask(w))._auto_cast(t)), -1)
self.assertEqual(int(ut.fromPy(mask(w))._signed()), -1)
def test_8b_and(self, t=int8_t):
low, up, intLow, intUp = self.getMinMaxVal(t)
ut = Bits(t.bit_length())
m = t.all_mask()
v = t.fromPy(-1)
self.assertEqual(v & ut.fromPy(m), -1)
self.assertEqual(v & ut.fromPy(0), 0)
self.assertEqual(v & ut.fromPy(1), 1)
self.assertEqual(low & up, 0)
self.assertEqual(low & -1, intLow)
self.assertEqual(up & ut.fromPy(m), intUp)
def test_BitsFromPyEnum(self):
class PyEnumCls(Enum):
A = 1
B = 3
C = 4
t = Bits(2)
self.assertValEq(t.fromPy(PyEnumCls.A), 1)
self.assertValEq(t.fromPy(PyEnumCls.B), 3)
with self.assertRaises(ValueError):
t.fromPy(PyEnumCls.C)
def test_BitsIndexTypes(self):
t = Bits(8)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v[object()]
with self.assertRaises(IndexError):
v[9:]
with self.assertRaises(IndexError):
v[:-1]
p = Param(2)
self.assertIsInstance(v[p], RtlSignalBase)
self.assertEqual(v[p]._dtype.bit_length(), 1)
p2 = p._downto(0)
self.assertIsInstance(v[p2], RtlSignalBase)
self.assertEqual(v[p2]._dtype.bit_length(), 2)
p3 = Param("abc")
with self.assertRaises(TypeError):
v[p3]
a = RtlSignal(None, "a", BIT)
a._const = False
with self.assertRaises(TypeError):
v[p] = a
with self.assertRaises(TypeError):
v[a] = p
v[p] = 1
self.assertEqual(v, 5)
v[p2] = 2
self.assertEqual(v, 6)
with self.assertRaises(TypeError):
v[hInt(None)] = 2
v[:] = 0
self.assertEqual(v, 0)
v[2] = 1
self.assertEqual(v, 4)
v[3:] = p
self.assertEqual(v, 2)
v._setitem__val(hInt(None), hInt(1))
with self.assertRaises(ValueError):
int(v)
with self.assertRaises(TypeError):
v[hStr("asfs")]
def test_8b_or(self, t=int8_t):
ut = Bits(t.bit_length())
m = t.all_mask()
low, up, intLow, intUp = self.getMinMaxVal(t)
v = t.fromPy(-1)
self.assertEqual(v | ut.fromPy(m), -1)
self.assertEqual(v | ut.fromPy(0), -1)
self.assertEqual(low | ut.fromPy(m), -1)
self.assertEqual(low | ut.fromPy(0), intLow)
self.assertEqual(up | ut.fromPy(m), -1)
self.assertEqual(up | ut.fromPy(0), intUp)
def test_array_eq_neq(self):
t = Bits(8)[5]
v0 = t.fromPy(range(5))
v1 = t.fromPy({0: 10, 1: 2})
v2 = t.fromPy([1, 2, 3, 4, 5])
self.assertTrue(v0._eq(v0))
with self.assertRaises(ValueError):
self.assertNotEqual(v0, v1)
self.assertNotEqual(v0, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v2)
with self.assertRaises(ValueError):
self.assertNotEqual(v1, v1)
self.assertTrue(v2, v2)
def test_8b_ne(self, t=int8_t):
ut = Bits(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
self.assertFalse(t.fromPy(-1) != -1)
self.assertFalse(t.fromPy(0) != 0)
self.assertFalse(up != up)
self.assertFalse(low != low)
self.assertTrue(t.fromPy(0) != -1)
self.assertTrue(t.fromPy(-1) != 0)
self.assertTrue(up != low)
self.assertTrue(low != up)
with self.assertRaises(TypeError):
t.fromPy(0) != ut.fromPy(0)
def test_8b_eq(self, t=int8_t):
ut = Bits(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
self.assertTrue(t.fromPy(-1)._eq(-1))
self.assertTrue(t.fromPy(0)._eq(0))
self.assertTrue(up._eq(up))
self.assertTrue(low._eq(low))
self.assertFalse(t.fromPy(0)._eq(-1))
self.assertFalse(t.fromPy(-1)._eq(0))
self.assertFalse(up._eq(low))
self.assertFalse(low._eq(up))
with self.assertRaises(TypeError):
t.fromPy(0)._eq(ut.fromPy(0))
def test_8b_lt(self, t=int8_t):
ut = Bits(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
self.assertFalse(t.fromPy(-1) < -1)
self.assertFalse(t.fromPy(0) < 0)
self.assertFalse(t.fromPy(1) < 1)
self.assertFalse(up < up)
self.assertFalse(low < low)
self.assertFalse(t.fromPy(0) < -1)
self.assertTrue(t.fromPy(-1) < 0)
self.assertFalse(up < low)
self.assertTrue(low < up)
with self.assertRaises(TypeError):
t.fromPy(0) < ut.fromPy(0)
def test_8b_gt(self, t=int8_t):
ut = Bits(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
self.assertFalse(t.fromPy(-1) > -1)
self.assertFalse(t.fromPy(0) > 0)
self.assertFalse(t.fromPy(1) > 1)
self.assertFalse(up > up)
self.assertFalse(low > low)
self.assertTrue(t.fromPy(0) > -1)
self.assertFalse(t.fromPy(-1) > 0)
self.assertTrue(up > low)
self.assertFalse(low > up)
with self.assertRaises(TypeError):
t.fromPy(0) > ut.fromPy(0)
def test_8b_mul(self, t=int8_t):
w = t.bit_length()
low, up, _, _ = self.getMinMaxVal(t)
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1) * t.fromPy(-1)), 1)
self.assertEqual(int(t.fromPy(0) * t.fromPy(-1)), 0)
self.assertEqual(int(ut.fromPy(0) * ut.fromPy(1)), 0)
self.assertEqual(int(ut.fromPy(mask(w)) * ut.fromPy(2)), (mask(w) << 1) & mask(w))
self.assertEqual(int(t.fromPy(-1) * ut.fromPy(2)), -2)
self.assertEqual(low * t.fromPy(2), 0)
self.assertEqual(up * t.fromPy(2), -2)
m = up * t.fromPy(None)
self.assertEqual(valToInt(m), None)
def test_BitsMulInvalidType(self):
t = Bits(8)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v * "a"
