def connectPort(self, port: BramPort_withoutClk, mem: RtlSignal):
If(self.clk._onRisingEdge() & port.en,
If(port.we,
mem[port.addr](port.din)
),
port.dout(mem[port.addr])
)
def connect_port(clk: RtlSignal, port: BramPort_withoutClk, mem: RtlSignal):
if port.HAS_R and port.HAS_W:
If(clk._onRisingEdge(),
If(port.en,
*RamSingleClock.mem_write(mem, port),
port.dout(mem[port.addr])
)
)
elif port.HAS_R:
If(clk._onRisingEdge(),
If(port.en,
port.dout(mem[port.addr])
)
)
elif port.HAS_W:
If(clk._onRisingEdge(),
If(port.en,
*RamSingleClock.mem_write(mem, port),
)
)
else:
raise AssertionError("Bram port has to have at least write or read part")
def connectPort(self, port: BramPort_withoutClk, mem: RtlSignal):
If(self.clk._onRisingEdge() & port.en,
If(port.we, mem[port.addr](port.din)), port.dout(mem[port.addr]))