def _declr(self): HandshakeSync._declr(self) args = HObjList() for a in self._exception.hw_args: _a = monitor_of(a) args.append(_a) self.args = args
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) self.index = VectSignal(self.INDEX_WIDTH) if self.WAY_CNT > 1: self.way = VectSignal(log2ceil(self.WAY_CNT - 1)) HandshakeSync._declr(self)
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.append = Signal() self.data = VectSignal(self.DATA_WIDTH) # an address where the item was stored self.addr_ret = VectSignal(self.ADDR_WIDTH, masterDir=DIRECTION.IN) HandshakeSync._declr(self)
def _declr(self): self.addr = VectSignal(self.MAIN_STATE_INDEX_WIDTH) if self.MAIN_STATE_T is not None: self.data = HdlType_to_Interface().apply(self.MAIN_STATE_T) if self.TRANSACTION_STATE_T is not None: self.transaction_state = HdlType_to_Interface().apply( self.TRANSACTION_STATE_T) HandshakeSync._declr(self)
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) # rem is number of bits in last word which is valid - 1, # if rem == 0 it means all bytes are valid self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) if self.SHIFT_OPTIONS != (0, ): self.shift = VectSignal(log2ceil(len(self.SHIFT_OPTIONS))) if self.HAS_PROPAGATE_LAST: self.propagateLast = Signal() HandshakeSync._declr(self)
def _declr(self): self.id = VectSignal(self.ID_WIDTH) self.addr = VectSignal(self.ADDR_WIDTH) # len is number of words -1 self.len = VectSignal(log2ceil(self.MAX_LEN)) # rem is number of bits in last word which is valid - 1 self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) HandshakeSync._declr(self)
def _declr(self): if self.SHIFT_OPTIONS != (0, ): # The encoded value of how many bytes should be the data from input write data be shifted # in order to fit the word on output write bus self.shift = VectSignal(log2ceil(len(self.SHIFT_OPTIONS))) # last word can be canceled because the address can have some offset which could # potentially spot new word but due to limited transaction size (using req.rem) # this should not happen, this flags provides this information self.drop_last_word = Signal() HandshakeSync._declr(self)
def _declr(self): Axi_id._declr(self) self.found = Signal() self.addr = VectSignal(self.ADDR_WIDTH) if self.WAY_CNT > 1: self.way = VectSignal(log2ceil(self.WAY_CNT - 1)) if self.TAG_T is not None: self.tags = HObjList(HdlType_to_Interface().apply(self.TAG_T) for _ in range(self.WAY_CNT)) HandshakeSync._declr(self)
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) self.addr = VectSignal(self.ADDR_WIDTH) assert self.MAX_LEN >= 0, self.MAX_LEN if self.MAX_LEN > 0: self.len = VectSignal(log2ceil(self.MAX_LEN + 1)) # rem is number of bytes in last word which are valid - 1 self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) HandshakeSync._declr(self)
def _declr(self): HandshakeSync._declr(self) if self.LOOKUP_ID_WIDTH: self.lookupId = VectSignal(self.LOOKUP_ID_WIDTH) if self.LOOKUP_HASH: self.hash = VectSignal(self.HASH_WIDTH) if self.LOOKUP_KEY: self.key = VectSignal(self.KEY_WIDTH) if self.DATA_WIDTH: self.data = VectSignal(self.DATA_WIDTH) self.found = Signal() self.occupied = Signal()
def _declr(self): # rem is number of bits in last word which is valid - 1 self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) self.propagateLast = Signal() HandshakeSync._declr(self)
def _declr(self): self.id = VectSignal(self.ID_WIDTH) HandshakeSync._declr(self)
def _declr(self): self.isLast = Signal() HandshakeSync._declr(self)
def _declr(self): assert self.T is not None self.data = HdlType_to_Interface().apply(self.T) HandshakeSync._declr(self)
def _declr(self): self.opcode = VectSignal(Mdio.OP_W) # R/W self.addr = MdioAddr() self.wdata = VectSignal(Mdio.D_W) HandshakeSync._declr(self)
def _declr(self): self.a = VectSignal(self.DATA_WIDTH) self.b = VectSignal(self.DATA_WIDTH) HandshakeSync._declr(self)
def _declr(self): HandshakeSync._declr(self) if self.LOOKUP_ID_WIDTH: self.lookupId = VectSignal(self.LOOKUP_ID_WIDTH) self.key = VectSignal(self.KEY_WIDTH)
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH, masterDir=DIRECTION.IN) self.data = VectSignal(self.DATA_WIDTH) HandshakeSync._declr(self)
def _declr(self): HandshakeSync._declr(self) if self.KEY_WIDTH: self.key = VectSignal(self.KEY_WIDTH, masterDir=DIRECTION.IN) self.index = VectSignal(self.INDEX_WIDTH)
def _declr(self): HandshakeSync._declr(self) if self.KEY_WIDTH: self.key = VectSignal(self.KEY_WIDTH) self.index = VectSignal(self.INDEX_WIDTH)
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) self.addr = VectSignal(self.ADDR_WIDTH) HandshakeSync._declr(self)